Tunneling Current Variations in Small-Sized Devices Based on a Compact Threshold Voltage Model
Source abstract
Abstract
Accurate modeling of threshold voltage is necessary in the integrated circuit design of strained silicon devices. Thoroughly researching the factors that affect threshold voltage and establishing a more precise threshold voltage model, can provide essential theoretical support for integrated circuit design. By solving a Poisson equation, in this paper, we demonstrate a comprehensive physical model for the threshold voltage of strained Si NMOSFETs using the gradual channel approximation theory and a quasi-two-dimensional analysis. The model investigates the physical effects such as short-channel, narrow-channel, non-uniform doping, and drain-induced barrier lowering effects on the threshold voltage. After substituting the extracted parameters into the model, a comparison was made with experimental results to validate the accuracy and correctness of the established model. Additionally, variations in the tunneling current of small-sized devices were studied. The two models provide essential references for the analysis and design of strained Si large-scale integrated circuits.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Silicon Carbide Semiconductor Technologies
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Information and Control Engineering, Qingdao University of Technology, Qingdao 266520, China
School of Science, Yanshan University, Qinhuangdao 066000, China
Funding
Fujian Provincial Key Laboratory of Higher Education Open Research Projects
References (17)
Show source-provided references
1. Deep submicron CMOS based on silicon germanium technology10.1109/16.502123 ↗
2. Dependences of the hole mobility in the strained Si pMOSFET and gated Hall bars formed on SiGe/Si(110) on the channel direction and the strained Si thickness10.1016/j.jcrysgro.2021.126246 ↗
3. Two-dimensional threshold voltage model of sub-100 nm strained-Si/SiGe nMOSFET10.7498/aps.60.077106 ↗
4. Study of physically modeling for small-scaled strained Si nMOSFET10.7498/aps.60.098501 ↗
5. The Effect of γ-ray Total Dose Irradiation on the Gate Tunneling Current of Uniaxial Strain Si Nanoscale n-type Metal Oxide Semiconductor Field Effect Transistor
6. Implicit Analytical Surface/Interface Potential Solutions for Modeling Strained-Si MOSFETs10.1109/TED.2006.885520 ↗
7. Trap assisted tunneling and its effect on subthreshold swing of tunnel field effect transistors10.1109/TED.2016.2603468 ↗
8. Estimating Lateral Straggling of Impurity Profiles of Ions Implanted Into Crystalline Silicon10.1109/16.974707 ↗
9. Two-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs10.1049/iet-cds.2017.0046 ↗
10. Arora, N. (2007). MOSFET Modeling for VLSI Simulation, Springer. [1st ed.].10.1142/6157 ↗
11. Xu, S.L., Xie, M.X., and Zhang, Z.F. (2007). SiGe Microelectronics Technology, National Defense Industry Press. [1st ed.].
12. Valence band structure of biaxial strained Germanium for hole transport calculation10.1080/00268976.2022.2074561 ↗
13. Yannis, T., and Colin, M. (2011). Operation and Modeling of the MOS Transistor, Oxford University Press. [3rd ed.].
14. Substrate bias effects on drain-induced barrier lowering in short channel PMOS devices at 77 K10.1109/16.55758 ↗
15. An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides10.1109/TED.2008.924443 ↗
16. Mukhopadhyay, S., Raychowdhury, A., and Roy, K. (2003, January 9). Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. Proceedings of the DAC2003, Anaheim, CA, USA.10.1145/775832.775877 ↗
17. Gate Tunneling Current Model of Scaled Strained Si n -MOSFET with Drain Induced Barrier Lowering Effects10.1166/jno.2017.2100 ↗