The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology
Source abstract
Abstract
To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.
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Research context
OpenAlex topics: Radio Frequency Integrated Circuit Design · Advancements in PLL and VCO Technologies · Analog and Mixed-Signal Circuit Design
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Affiliations
Department of Digital Electronics, Dealim University College, 29 Imgok-ro, Dongan-gu, Anyang-si, Gyeonggi-do 13916, Korea
Department of Electrical and Computer Engineering, Sungkyunkwan University, 2066 Seobu-ro, Jangan-gu, Suwon, Gyeonggi-do 16419, Korea
References (18)
Show source-provided references
1. Balteanu, F. (2019, January 3–6). RF Front End Module Architectures for 5G. Proceedings of the BICMOS and Compound semiconductor Integrated Circuits and Technology Symposium, Nashville, TN, USA.10.1109/BCICTS45179.2019.8972735 ↗
2. MM-Wave Phased Array Quasi-Yagi Antenna for the Upcomming 5G Cellular Communications10.3390/app9050978 ↗
3. Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers10.1109/JSSC.2020.2987691 ↗
4. Arnaud, F., Thean, A., Eller, M., Lipinski, M., Teh, Y.W., Ostermayr, M., Kang, K., Kim, N.S., Ohuchi, K., and Han, J.-P. (2009, January 7–9). Competitivie and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications. Proceedings of the International Electron Devices Meeting, Baltimore, MD, USA.10.1109/IEDM.2009.5424255 ↗
5. A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS10.1109/LSSC.2020.3009973 ↗
6. Park, B., Jeong, D., Kim, J., Cho, Y., Moon, K., and Kim, B. (2016, January 22–27). Highly Linear CMOS Power Amplifier for mm-Wave Applications. Proceedings of the MTT-S International Microwave Symposium, San Francisco, CA, USA.10.1109/MWSYM.2016.7540024 ↗
7. Juneja, S., Pratap, R., and Sharma, R. (2020). Semiconductor Technologies for 5G Implementation at Millimeter Wave Frequencies—Design Challenges and Current State of Work. Enginnering Sci. Technol. Int. J.10.1016/j.jestch.2020.06.012 ↗
8. A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology10.1109/JSSC.2017.2747758 ↗
9. A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS10.1109/JSSC.2019.2938132 ↗
10. Suarez, G., and Dumonthier, J.J. (2020). Radiation Hardened Input/Output Expander with I2C and SPI Serial Interfaces. (10649949B1), U.S. Patent.
11. A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application10.1109/JSSC.2020.3005809 ↗
12. Chen, Z., Jiang, Z., Liu, Z., Cheng, Y., Zhang, L., Chen, D., Zhang, J., Sun, J., Dong, J., and Liu, P. (2018, January 10–15). A 256-QAM 39 GHz Dual-Channel Transceiver Chipset with LTCC Package for 5G Communication in 65 nm CMOS. Proceedings of the MTT-S International Microwave Symposium, Philadelphia, PA, USA.10.1109/MWSYM.2018.8439667 ↗
13. A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR10.1109/JSSC.2020.2995039 ↗
14. Wide Field-of-View Locating and Multimodal Vital Sign Monitoring Based on X-Band CMOS-Integrated Phased-Array Radar Sensor10.1109/TMTT.2020.2989284 ↗
15. A Full X-Band Phased-Array Transmit/Receive Module Chip in 65-nm CMOS Technology10.1109/ACCESS.2020.2988501 ↗
16. Niknejad, A.M., Emami, S., Heydari, B., Bohsali, M., and Asabi, E. (2007, January 14–17). Nanoscale CMOS for mm-Wave Applications. Proceedings of the Compound Semiconductor Integrated Circuits Symposium, Portland, OR, USA.10.1109/CSICS07.2007.37 ↗
17. Diwei, L., and Dizian, Z. (2019, January 13–15). A Low-Power Digital Control Core with High-Speed SPI Slave for Phased Array Application in 40 nm CMOS. Proceedings of the International Conference on Integrated Circuits, Technologies and Applications, Chengdu, China.
18. Diwei, L., and Dizian, Z. (2009, January 16–18). A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology. Proceedings of the 2009 Symposium on VLSI Circuits, Kyoto, Japan.