Sensorless PMSM Speed Control Using an FPGA-Implemented Unscented Kalman Filter

This paper presents the design and implementation of a field-programmable gate array (FPGA)-based System-on-Programmable-Chip (SoPC) architecture for sensorless speed control of permanent magnet synchronous motor (PMSM) drives. To enable real-time execution of the computationally intensive estimation stage, a parallelized Unscented Kalman Filter (UKF) is proposed for the joint estimation of rotor speed, position, and load torque. Unlike traditional sequential processor-based UKF implementations, the proposed parallel architecture simplifies the iterative process and significantly reduces computational latency and hardware resource utilization while preserving high estimation fidelity. This transformation reduces the number of sequential dependency stages within one estimation cycle and enables simultaneous execution of matrix operations using dedicated FPGA resources, thereby decreasing effective iteration latency. The complete control system comprises current regulators, a coordinate transformation module, a proportional–integral (PI) speed controller, and auxiliary functional blocks—all fully integrated within a single SoPC. The UKF estimator and control components are described using a hardware description language (HDL), enabling efficient hardware-level parallelism and real-time execution. The proposed system is validated through co-simulation and experimental verification on a Xilinx ZCU102 platform driving an inverter-fed PMSM. The results confirm correct real-time operation of the proposed architecture and demonstrate its feasibility for FPGA-based sensorless motor drive implementation. A detailed quantitative comparison with a fully sequential FPGA-based UKF implementation is identified as future work to further substantiate the reported latency reduction.