SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Source abstract
Abstract
Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase operation. Therefore, the gate-induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) to raise the channel potential, is employed. However, compared to bulk erase, the BTBT-based erase method requires a longer time to generate holes in the channel, leading to erase speed degradation. To address this issue, we propose a structure which enhances the erase speed by surrounding the bitline (BL) PAD with SiGe. In the case of a SiGe thickness (tSiGe) of 13 nm, the lower bandgap of SiGe increases the BTBT generation rate, boosting the channel potential rise at the end of the erase voltage ramp-up by 861% compared to the Si-only structure, while limiting the reduction in read on-current to within 4%. We modeled the voltage and electric field across the SiGe layer, as well as BTBT generation rate and GIDL current in the SiGe layer, by varying tSiGe, Ge composition ratio (SiGeX), and the voltage difference between VBL and VGIDL_TR.
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Research context
OpenAlex topics: Thin-Film Transistor Technologies · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul 01811, Republic of Korea
Funding
Korea government (Ministry of Science and ICT)
References (19)
Show source-provided references
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