A 60 GHz CMOS I/Q Receiver for High-Speed Wireless Communication System
Source abstract
Abstract
This paper presents a 60 GHz CMOS I/Q receiver for the high-speed wireless communication system. It consists of a low noise amplifier, single-to-differential (S2D) amplifier, passive mixer, buffer amplifier with passive I/Q generator, and wideband baseband amplifier (BBA) stage. The measured conversion gain of 51 dB is achieved. The baseband bandwidth of 300 MHz is achieved from 57 GHz to 60 GHz. The 90° tandem coupler was implemented for I/Q signal generation, which has a phase error of <7° and an amplitude imbalance of <2 dB from 55 to 62 GHz. The Marchand balun is used to convert the I/Q signal to the differential, which has a phase error of <4°. A 60 GHz CMOS I/Q receiver is designed and fabricated, using a commercial 40 nm CMOS bulk process. The size of the receiver is 2.02 × 1.45 mm2, including the pads. The circuit is operated from a 0.9 V supply. The power consumption is 172 mW at maximum gain mode.
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Research context
OpenAlex topics: Radio Frequency Integrated Circuit Design · Advancements in PLL and VCO Technologies · Microwave Engineering and Waveguides
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Electronic Engineering, Kwangwoon University, Seoul 01897, Korea
School of Electrical Engineering, Chung-Ang University, Seoul 06974, Korea
Funding
Korea government (MSIT)
References (18)
Show source-provided references
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