Structure and Principles of Operation of a Quaternion VLSI Multiplier
Source abstract
Abstract
The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository.
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Research context
OpenAlex topics: Cellular Automata and Applications · Cybersecurity and Information Systems · Numerical Methods and Algorithms
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Affiliations
Faculty of Computer Science and Information Technology, West Pomeranian University of Technology, 70-310 Szczecin, Poland
Faculty of Computing, Poznań University of Technology, ul. Piotrowo 3a, 60-965 Poznań, Poland
Faculty of Technology, The Jacob of Paradise University, 66-400 Gorzów Wielkopolski, Poland
Funding
Poznan University of Technology
References (40)
Show source-provided references
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