EH-YOLO: Dimensional Transformation and Hierarchical Feature Fusion-Based PCB Surface Defect Detection

Small surface defects in printed circuit boards (PCBs) severely affect the reliability of electronic devices, making PCB surface defect detection crucial for ensuring the quality of electronic products. However, the existing detection methods often struggle with insufficient accuracy and the inherent trade-off between detection precision and inference speed. To address these problems, we propose a novel ESDM-HNN-YOLO (EH-YOLO) network based on the improved YOLOv10 for efficient detection of small PCB defects. Firstly, an enhanced spatial-depth module (ESDM) is designed, which transforms spatial-dimensional features into depth-dimensional representations while integrating spatial attention module (SAM) and channel attention module (CAM) to highlight critical features. This dual mechanism not only effectively suppresses feature loss in micro-defects but also significantly enhances detection accuracy. Secondly, a hybrid neck network (HNN) is designed, which optimizes the speed–accuracy balance through hierarchical architecture. The hierarchical structure uses a computationally efficient weighted bidirectional feature pyramid network (BiFPN) to enhance multi-scale feature fusion of small objects in the shallow layer and uses a path aggregation network (PAN) to prevent feature loss in the deeper layer. Comprehensive evaluations on benchmark datasets (PCB_DATASET and DeepPCB) demonstrate the superior performance of EH-YOLO, achieving mAP@50-95 scores of 45.3% and 78.8% with inference speeds of 166.67 FPS and 158.73 FPS, respectively. These results significantly outperform existing approaches in both accuracy and processing efficiency.