A Review of Test Stimulus Compression Methods for Ultra-Large-Scale Integrated Circuits
Source abstract
Abstract
With the development of system-on-chip (SoC) and chiplet technology in the post-Moore era, an increasing number of chiplets are being integrated into a single chip. Consequently, the functions and complexity that can be realized are growing daily. Simultaneously, the volume of test data required for ultra-large-scale integrated circuits (ULSIs) has risen significantly. However, traditional automatic test equipment (ATE) is constrained by its data storage and bandwidth limitations, and its long technology iteration cycle. These cannot keep pace with the rapid development of design technology. This discrepancy leads to challenges in ULSI testing, such as excessively long test time and difficulties in completing the tests. Test compression technology can effectively address these issues by reducing the performance requirements of the test equipment, which in turn can lower test costs. This paper summarizes the classifications of chip test compression technology and, based on their current development, provides a detailed analysis of key technologies. It includes test compression-oriented coding methods, optimization of scan chain structures, and enhancements in coding for compression efficiency. Finally, a forward-looking perspective on the development of chip test compression technology is presented. The aim is to offer a reference for subsequent research in this field and related areas, as well as to provide technical support for the advancement of ULSI testing in the post-Moore era.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: VLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · VLSI and FPGA Design Techniques
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
National Elite Institute of Engineering, Northwestern Polytechnical University, Xi’an 710072, China
Beijing Microelectronics Technology Institute, Beijing 100076, China
China Astronautics Standards Institute, Beijing 100166, China
References (100+)
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