Parallel Implementations of ARIA on ARM Processors and Graphics Processing Unit
Source abstract
Abstract
The ARIA block cipher algorithm is Korean standard, IETF standard (RFC 5794), and part of the TLS/SSL protocol. In this paper, we present the parallel implementation of ARIA block cipher on ARMv8 processors and GPU. The ARMv8 processor is the latest 64-bit ARM architecture and supports ASIMD for parallel implementations. With this feature, 4 and 16 parallel encryption blocks are implemented to optimize the substitution layer of ARIA block cipher using four different Sboxes. Compared to previous works, the performance was improved by 2.76× and 8.73× at 4-plaintext and 16-plaintext cases, respectively. We also present optimal implementation on GPU architectures. GPUs are highly parallel programmable processors featuring maximum arithmetic and memory bandwidth. Optimal settings of ARIA block cipher implementation on GPU were analyzed using the Nsight Compute profiler provided by Nvidia. We found that using shared memory reduces the execution timing when performing substitution operations with Sbox tables. When using many threads with shared memory instead of global memory, it improves performance by about 1.08∼1.43×. Additionally, techniques using table expansion to minimize bank conflicts have been found to be inefficient when tables cannot be copied by the size of the bank. We measured the performance of ARIA block ciphers implemented with various settings. This represents an optimized GPU implementation of the ARIA block cipher.
Source: crossref · Quality: baseline
Research context
OpenAlex topics: Cryptographic Implementations and Security · Coding theory and cryptography · Chaos-based Image/Signal Encryption
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Division of IT Convergence Engineering, Hansung University, Seoul 02876, Republic of Korea
Funding
Hansung University
References (25)
Show source-provided references
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