An Optimized Method for Nonlinear Function Approximation Based on Multiplierless Piecewise Linear Approximation
Source abstract
Abstract
In this paper, we propose an optimized method for nonlinear function approximation based on multiplierless piecewise linear approximation computation (ML-PLAC), which we call OML-PLAC. OML-PLAC finds the minimum number of segments with the predefined fractional bit width of input/output, maximum number of shift-and-add operations, user-defined widths of intermediate data, and maximum absolute error (MAE). In addition, OML-PLAC minimizes the actual MAE as much as possible by iterating. As a result, under the condition of satisfying the maximum number of segments, the MAE can be minimized. Tree-cascaded 2-input and 3-input multiplexers are used to replace multi-input multiplexers in hardware architecture as well, reducing the depth of the critical path. The optimized method is applied to logarithmic, antilogarithmic, hyperbolic tangent, sigmoid and softsign functions. The results of the implementation prove that OML-PLAC has better performance than the current state-of-the-art method.
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Research context
OpenAlex topics: Numerical Methods and Algorithms · Digital Filter Design and Implementation · Blind Source Separation Techniques
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Affiliations
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
University of Chinese Academy of Sciences, Beijing 100049, China
References (30)
Show source-provided references
1. A retrospective and prospective view of approximate computing10.1109/JPROC.2020.2975695 ↗
2. Fixed-point square roots using L-b truncation10.1109/MSP.2011.942297 ↗
3. Generalized hyperbolic CORDIC and its logarithmic and exponential computation with arbitrary fixed base10.1109/TVLSI.2019.2919557 ↗
4. GH CORDIC-Based Architecture for Computing Nth Root of Single-Precision Floating-Point Number10.1109/TVLSI.2019.2959847 ↗
5. A digit-by-digit algorithm for mth root extraction10.1109/TC.2007.70764 ↗
6. Accelerating recurrent neural networks: A memory-efficient approach10.1109/TVLSI.2017.2717950 ↗
7. Nilsson, P., Shaik, A.U.R., Gangarajaiah, R., and Hertz, E. (2014, January 27–28). Hardware implementation of the exponential function using Taylor series. Proceedings of the 2014 NORCHIP, Tampere, Finland.10.1109/NORCHIP.2014.7004740 ↗
8. Log-MAP equivalent Chebyshev inequality based algorithm for turbo TCM decoding10.1049/el.2011.2141 ↗
9. Chong, Y.S., Goh, W.L., Ong, Y.S., Nambiar, V.P., and Do, A.T. (2021, January 4–7). Efficient Implementation of Activation Functions for LSTM accelerators. Proceedings of the 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapore.10.1109/VLSI-SoC53125.2021.9606971 ↗
10. Chinta, C., and Deshmukh, R.B. (2018, January 10–12). High speed most significant bit first truncated multiplier. Proceedings of the 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Bengaluru, India.10.1109/ICCCNT.2018.8494062 ↗
11. Chandrashekara, M., and Rohith, S. (2019, January 17–18). Design of 8 bit Vedic multiplier using Urdhva Tiryagbhyam sutra with modified carry save adder. Proceedings of the 2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), Bangalore, India.10.1109/RTEICT46194.2019.9016965 ↗
12. On the design of logarithmic multiplier using radix-4 booth encoding10.1109/ACCESS.2020.2985345 ↗
13. Efficient logarithmic converters for digital signal processing applications
14. Low cost hardware implementation of logarithm approximation10.1109/TVLSI.2010.2081387 ↗
15. Ellaithy, D.M., El-Moursy, M.A., Ibrahim, G.H., Zaki, A., and Zekry, A. (2017, January 10–13). Accurate Piecewise Uniform Approximation Logarithmic/Antilogarithmic Converters for GPU Applications. Proceedings of the 2017 29th International Conference on Microelectronics (ICM), Beirut, Lebanon.10.1109/ICM.2017.8268821 ↗
16. Qin, Z. (2020). Optimizations and Implementations for Key Components of Deep Neural Networks, Nanjing University.
17. A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function
18. A 231-MHz, 2.18-mW 32-bit logarithmic arithmetic unit for fixed-point 3-D graphics system10.1109/JSSC.2006.882887 ↗
19. An embedded stream processor core based on logarithmic arithmetic for a low-power 3-D graphics SoC10.1109/JSSC.2009.2016698 ↗
20. Double logarithmic arithmetic technique for low-power 3-D graphics applications10.1109/TVLSI.2017.2667714 ↗
21. Ellaithy, D.M., El-Moursy, M.A., Ibrahim, G.H., Zaki, A., and Zekry, A. (2017, January 5–8). Efficient Piecewise Non-Uniform Approximation Logarithmic and Antilogarithmic Converters. Proceedings of the 2017 International Conference on Advanced Control Circuits Systems (ACCS) Systems & 2017 International Conference on New Paradigms in Electronics & Information Technology (PEIT), Alexandria, Egypt.10.1109/ACCS-PEIT.2017.8303034 ↗
22. An optimized logarithmic converter with equal distribution of relative errors
23. A low-error, cost-efficient design procedure for evaluating logarithms to be used in a logarithmic arithmetic processor10.1109/TC.2015.2441696 ↗
24. Error-aware design procedure to implement hardware-efficient logarithmic circuits
25. A universal method of linear approximation with controllable error for the efficient implementation of transcendental functions10.1109/TCSI.2019.2939563 ↗
26. PLAC: Piecewise linear approximation computation for all nonlinear unary functions10.1109/TVLSI.2020.3004602 ↗
27. Ultralow-latency VLSI architecture based on a linear approximation method for computing Nth roots of floating-point numbers10.1109/TCSI.2020.3038417 ↗
28. PWL-based architecture for the logarithmic computation of floating-point numbers10.1109/TVLSI.2021.3081572 ↗
29. ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation10.1109/TCSI.2021.3133931 ↗
30. Chang, C.-H., Zhang, E.-H., and Huang, S.-H. (2019, January 3–6). Softsign Function Hardware Implementation Using Piecewise Linear Approximation. Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Taipei, Taiwan.10.1109/ISPACS48206.2019.8986274 ↗