High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip
Source abstract
Abstract
This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.
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Research context
OpenAlex topics: Advancements in PLL and VCO Technologies · Analog and Mixed-Signal Circuit Design · CCD and CMOS Imaging Sensors
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Key Laboratory of Electronic Equipment Structure Design, Ministry of Education, School of Electro-Mechanical Engineering, Xidian University, Xi’an 710071, China
Funding
the National Science Foundation of China · the Fundamental Research Funds for the Central Universities of China
References (14)
Show source-provided references
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