Low-Power 8T SRAM Compute-in-Memory Macro for Edge AI Processors
Source abstract
Abstract
The traditional Von Neumann architecture creates bottlenecks due to data movement. The compute-in-memory (CIM) architecture performs computations within memory bit-cell arrays, enhancing computational performance. Edge devices utilizing artificial intelligence (AI) address real-time problems and have established themselves as groundbreaking technology. The 8T structure proposed in this paper has strengths over other existing structures in that it better withstands environmental changes within the SRAM and consumes lower power during memory operation. This structure minimizes reliance on complex ADCs, instead utilizing a simplified voltage differential approach for multiply-and-accumulate (MAC) operations, which enhances both power efficiency and stability. Based on these strengths, it can achieve higher battery efficiency in AI edge devices and improve system performance. The proposed integrated circuit was simulated in a 90 nm CMOS process and operated on a 1 V supply voltage.
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Research context
OpenAlex topics: Advanced Memory and Neural Computing · Interconnection Networks and Systems · CCD and CMOS Imaging Sensors
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Nano & Semiconductor Engineering, Tech University of Korea, Siheung 15073, Republic of Korea
References (11)
Show source-provided references
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