Enhancing Field Multiplication in IoT Nodes with Limited Resources: A Low-Complexity Systolic Array Solution
Source abstract
Abstract
Security and privacy concerns pose significant obstacles to the widespread adoption of IoT technology. One potential solution to address these concerns is the implementation of cryptographic protocols on resource-constrained IoT edge nodes. However, the limited resources available on these nodes make it challenging to effectively deploy such protocols. In cryptographic systems, finite-field multiplication plays a pivotal role, with its efficiency directly impacting overall performance. To tackle these challenges, we propose an innovative and compact bit-serial systolic layout specifically designed for Montgomery multiplication in the binary-extended field. This novel multiplier structure boasts regular cell architectures and localized communication connections, making it particularly well suited for VLSI implementation. Through a comprehensive complexity analysis, our suggested design demonstrates significant improvements in both area and area–time complexities when compared to existing competitive bit-serial multiplier structures. This makes it an ideal choice for cryptographic systems operating under strict area utilization constraints, such as resource-constrained IoT nodes and tiny embedded devices.
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Research context
OpenAlex topics: Coding theory and cryptography · Cryptography and Residue Arithmetic · Cryptography and Data Security
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Computer Engineering Department, College of Computer Engineering and Sciences, Prince Sattam bin Abdulaziz University, Al-Kharj 16278, Saudi Arabia
Electrical and Computer Engineering Department, University of Victroia, Victoria, BC V8P 5C2, Canada
Funding
Prince Sattam Bin Abdulaziz University
References (38)
Show source-provided references
1. Blahut, R.E., Katz, J., van Oorschot, P.C., and Vanstone, S.A. (1996). Handbook of Applied Cryptography, CRC Press.
2. Blahut, R.E. (1983). Theory and Practice of Error Control Codes, Addison-Wesley.
3. Pöpper, C. (2024, January 5–8). Applied Cryptography and Network Security. Proceedings of the 22nd International Conference, ACNS 2024, Abu Dhabi, United Arab Emirates. Proceedings, Part I.10.1007/978-3-031-54776-8 ↗
4. Tang, Q. (2024, January 15–17). Public-Key Cryptography–PKC 2024. Proceedings of the 27th IACR International Conference on Practice and Theory of Public-Key Cryptography, Sydney, NSW, Australia. Proceedings, Part II.10.1007/978-3-031-57722-2 ↗
5. Seedorf, J., Mazhar, K., Schwabe, F., and Omerovic, I. (2022). Online-Labs in Education, Nomos Verlagsgesellschaft mbH & Co. KG.
6. A common-multiplicand method to the montgomery algorithm for speeding up exponentiation10.1016/S0020-0190(98)00031-3 ↗
7. Linear systolic multiplier/squarer for fast exponentiation10.1016/S0020-0190(00)00131-9 ↗
8. Song, L., and Parhi, K.K. (1996, January 19–23). Efficient finite field serial/parallel multiplication. Proceedings of the IEEE 1996 International Conference on Application-Specific Architectures and Processors, Chicago, IL, USA.
9. High-speed hybrid-double multiplication architectures using new serial-out bit-level mastrovito multipliers10.1109/TC.2015.2456023 ↗
10. Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring10.1587/elex.16.20190600 ↗
11. Efficient unified semi-systolic arrays for multiplication and squaring over gf(2m)10.1587/elex.14.20170458 ↗
12. Efficient bit-parallel systolic architecture for multiplication and squaring over gf(2m)10.1587/elex.14.20171195 ↗
13. Efficient parallel and serial systolic structures for multiplication and squaring over gf(2m)10.1109/CJECE.2019.2900087 ↗
14. A comparison of vlsi architecture of finite field multipliers using dual, normal, or standard bases10.1109/12.2212 ↗
15. Bit-parallel finite field multiplier and squarer using polynomial basis10.1109/TC.2002.1017695 ↗
16. Low-latency bit-pararallel systolic multiplier for irreducible xm + xn + 1 with GCD(m, n) = 1
17. Ringed bit-parallel systolic multipliers over a class of fields gf(2m)10.1016/j.vlsi.2004.10.001 ↗
18. Versatile multiplier architectures in gf(2k) fields using the montgomery multiplication algorithm10.1016/j.vlsi.2007.07.004 ↗
19. Kim, K.-W., Lee, H.-H., and Kim, S.-H. (2017). Proceedings of the 7th International Conference on Emerging Databases, LNEE 461, Springer.
20. Resource and delay efficient polynomial multiplier over finite fields gf (2m)
21. Low complexity systolic Montgomery multiplication over finite fields gf (2m)
22. Imaña, J.L., Piñuel, L., Kuo, Y.-M., Ruano, O., and García-Herrero, F. (2024). IEEE Transactions on Circuits and Systems II: Express Briefs, IEEE.
23. High-performance unified modular multiplication algorithm and hardware architecture over gf(2m)10.1016/j.vlsi.2023.102124 ↗
24. A dual basis bit serial systolic multiplier for gf(2m)10.1016/0167-9260(95)00007-3 ↗
25. A semi-systolic montgomery multiplier over gf(2m)10.1587/elex.12.20150769 ↗
26. Efficient systolic modular multiplier/squarer for fast exponentiation over gf(2m)10.1587/elex.12.20150222 ↗
27. An efficient reconfigurable multiplier architecture for galois field gf(2m)10.1016/S0026-2692(03)00172-1 ↗
28. Improved throughput bit-serial multiplier for gf(2m) fields10.1016/j.vlsi.2008.07.003 ↗
29. Digit-serial systolic multiplier for finite fields gf(2m)10.1049/ip-cdt:19981906 ↗
30. Hutter, M., Grobschald, J., and Kamenje, G.-A. (2003, January 28–30). A versatile and scalable digit-serial/parallel multiplier architecture for finite fields gf(2m). Proceedings of the 2003 4th International Conference on InformationTechnology: Coding and Computing (ITTCC2003), Las Vegas, NV, USA.
31. Low-energy digit serial/parallel finite field multipliers10.1023/A:1008013818413 ↗
32. A digit-serial multiplier for finite field GF(2m)10.1109/TVLSI.2004.842923 ↗
33. Hariri, A., and Reyhani-Masoleh, A. (2008, January 6–9). Digit-serial structures for the shifted polynomial basis multiplication over binary extension fields. Proceedings of the LNCS Intl Workshop Arithmetic of Finite Fields (WAIFI), Siena, Italy.10.1007/978-3-540-69499-1_9 ↗
34. Gebali, F. (2011). Algorithms and Parallel Computers, John Wiley.10.1002/9780470932025 ↗
35. New systolic array architecture for finite field division10.1587/elex.15.20180255 ↗
36. Scalable digit-serial processor array architecture for finite field division10.1016/j.mejo.2019.01.011 ↗
37. Low-space bit-serial systolic array architecture for interleaved multiplication over gf (2m)10.1049/cdt2.12026 ↗
38. Reyhani-Masoleh, A. (2008, January 10–13). A new bit-serial architecture for field multiplication using polynomial bases. Proceedings of the 7th International Workshop Cryptographic Hardware Embedded Systems (CHES 2008), Washington, DC, USA.