Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber
Source abstract
Abstract
This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feedback number theoretic transform multiplier dedicating for Kyber parameter set and deploying this multiplier in the Kyber architecture, the key generation, encryption, and decryption operations are accelerated substantially. Furthermore, the proposed architecture offers the best value of area-time product in comparison with existing approaches. The implementation results on Xilinx Vivado targeted for Virtex-7 FPGA board demonstrate that the proposed Kyber cryptoprocessor completes encryption and decryption operations in approximately 57.5 μs at the highest frequency of 226 MHz. Furthermore, the area-time product value when using the proposed Kyber architecture is improved by at least twofold compared with existing architectures.
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Research context
OpenAlex topics: Cryptography and Residue Arithmetic · Cryptographic Implementations and Security · Cryptography and Data Security
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Information and Communication Engineering, Inha University, Incheon 22212, Korea
Funding
Ministry of Science and ICT (MSIT) · National Research Foundation of Korea (NRF) · IITP grant funded by the Korea government (MSIT)
References (22)
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