Logic Design Within Memristive Memories Using Memristor-Aided loGIC (MAGIC)
Source abstract
Abstract
Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit ( MPU ). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory—the transpose memory , which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 $\times$ faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2 $\times$ ) and energy (10 $\times$ ), with similar area.
Source: openalex_inverted_index · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neuroscience and Neural Engineering
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (57)
Show source-provided references
1. 10.1109/LED.2011.217131710.1109/LED.2011.2171317 ↗
2. 10.1109/TCSII.2015.243353610.1109/TCSII.2015.2433536 ↗
3. 10.1038/nnano.2008.16010.1038/nnano.2008.160 ↗
4. 10.1109/TED.2011.215800410.1109/TED.2011.2158004 ↗
5. SPICE model of memristor with nonlinear dopant drift
6. 10.1109/ESSCIRC.2007.443031010.1109/ESSCIRC.2007.4430310 ↗
7. 10.1109/TCSI.2012.221571410.1109/TCSI.2012.2215714 ↗
8. 10.1109/ISCAS.2011.593794210.1109/ISCAS.2011.5937942 ↗
9. 10.1063/1.323650610.1063/1.3236506 ↗
10. 10.1109/CNNA.2010.543030410.1109/CNNA.2010.5430304 ↗
11. 10.1063/1.352452110.1063/1.3524521 ↗
12. 10.1038/nnano.2012.24010.1038/nnano.2012.240 ↗
13. Memristor material engineering: From flash memory replacement towards a universal memory
14. 10.1109/PROC.1976.1009210.1109/PROC.1976.10092 ↗
15. 10.1109/TCT.1971.108333710.1109/TCT.1971.1083337 ↗
16. 10.1109/TCSII.2014.235729210.1109/TCSII.2014.2357292 ↗
17. NAND flash solid state storage for the enterprise—An in-depth look at reliability
18. 10.1109/IRPS.2014.686115810.1109/IRPS.2014.6861158 ↗
19. 10.1007/s00339-011-6264-910.1007/s00339-011-6264-9 ↗
20. 10.1109/JSSC.2011.214843010.1109/JSSC.2011.2148430 ↗
21. 10.1088/0957-4484/22/48/48520310.1088/0957-4484/22/48/485203 ↗
22. 10.1073/pnas.080664210610.1073/pnas.0806642106 ↗
23. A 130.7 mm 2 2-layer 32Gb ReRAM memory device in 24nm technology
24. 10.1109/TNANO.2014.229955810.1109/TNANO.2014.2299558 ↗
25. 10.1109/54.78583810.1109/54.785838 ↗
26. 10.1016/j.mejo.2015.03.02110.1016/j.mejo.2015.03.021 ↗
27. 10.1109/JETCAS.2015.239821710.1109/JETCAS.2015.2398217 ↗
28. 10.1109/TC.2011.2610.1109/TC.2011.26 ↗
29. 10.1145/2422094.242210310.1145/2422094.2422103 ↗
30. 10.1038/nmat274810.1038/nmat2748 ↗
31. On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex
32. 10.1109/TNNLS.2014.238339510.1109/TNNLS.2014.2383395 ↗
33. 10.1038/nmat341510.1038/nmat3415 ↗
34. 10.1109/ISSCC.2014.675732310.1109/ISSCC.2014.6757323 ↗
35. 10.1088/0957-4484/23/30/30520510.1088/0957-4484/23/30/305205 ↗
36. 10.1109/TNANO.2003.82080410.1109/TNANO.2003.820804 ↗
37. 10.1145/1084748.108475010.1145/1084748.1084750 ↗
38. 10.1007/3-540-31514-4_1710.1007/3-540-31514-4_17 ↗
39. 10.1109/VLSID.2015.9410.1109/VLSID.2015.94 ↗
40. 10.1109/TNANO.2010.204155610.1109/TNANO.2010.2041556 ↗
41. 10.1109/NANOARCH.2009.522635610.1109/NANOARCH.2009.5226356 ↗
42. 10.1021/nl901874j10.1021/nl901874j ↗
43. Nonvolatile memristor memory: Device characteristics and design implications
44. 10.1109/ICCD.2011.608138910.1109/ICCD.2011.6081389 ↗
45. 10.1038/nature0894010.1038/nature08940 ↗
46. 10.1109/TVLSI.2013.228213210.1109/TVLSI.2013.2282132 ↗
47. MRL—Memristor ratioed logic
48. 10.1145/284508410.1145/2845084 ↗
49. 10.1021/nl904092h10.1021/nl904092h ↗
50. 10.1109/JPROC.2011.216569010.1109/JPROC.2011.2165690 ↗
51. worst-case analysis of a resistor memory matrix10.1109/T-C.1969.222549 ↗
52. Design implications of memristor-based RRAM cross-point structures
53. 10.1109/TNANO.2012.218830210.1109/TNANO.2012.2188302 ↗
54. An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device
55. 10.1109/LED.2011.216329210.1109/LED.2011.2163292 ↗
56. 10.1109/ISIT.2013.662020710.1109/ISIT.2013.6620207 ↗
57. 10.1016/j.mejo.2012.10.00110.1016/j.mejo.2012.10.001 ↗