Fabrication and Comparison of Bumpless Wafer-on-Wafer Integration and Bump-Containing Chip-on-Chip Integration

This paper develops a bumpless wafer-on-wafer (WoW) memory integration approach in order to increase its throughput and reliability without sacrificing the electrical and mechanical performances compared to the bump-containing chip-on-chip (CoC) integration. The features are that through silicon vias are bottom-up filled after multilayer wafers bonding and connected to the predeposited redistribution layers on the front side of each wafer simultaneously. A given mass of four-layer bumpless WoW integration samples and bump-containing CoC integration samples is fabricated. The electrical testing, X-ray inspection, cross-section observation, stress testing, and thermal cycling testing are employed in order to compare the characterization of the two integration approaches. All test results support that there is a better performance, higher throughput, and lower cost in the proposed bumpless WoW integration approach, which indicates that this proposed approach may be a good candidate for memories-stacking application.