DataVXIEEE Transactions on Components, Packaging and Manufacturing TechnologyPaper
journal article·2017-10

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Dewen Tian, Nelson Fan, Eric Kuah, Wu Kai, Margie Li, J. Hao, Yiu Ming Cheung, Zhang Li, Kim Hwee Tan, Rozalia Beica, Thomas Taylor, Cheng-Ta Ko, Henry Yang, Yu-Hua Chen, Sze Pei Lim, Ning Cheng Lee, Jiang Ran, Cao Xi, Koh Sau Wee, Qingxiang Yong

IEEE Transactions on Components, Packaging and Manufacturing Technology· Volume 7· Issue 10
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Source abstract

Abstract

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.
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Research context

OpenAlex topics: 3D IC and TSV technologies · Electronic Packaging and Soldering Technologies · Electromagnetic Compatibility and Noise Suppression

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

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