Electrical Design and Techniques for an Embedded High-Pin-Count LSI Chip Package

In order to achieve the excellent electrical performance, as well as low warpage and high heat removal, electrical design techniques for an ultrathin large-scale integration (LSI) package embedding a high-pin-count LSI chip in the thin package substrate have been developed. The embedded chip package we designed is 27 mm × 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip-chip ball grid array package using the same chip, even though the package size is the same. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick Cu plate attached to the LSI chip's backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. In addition, it functioned as a shield component and results in electromagnetic interference suppression. Our design for a fully operative LSI chip with approximately 1500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip. Finally, the advantage of a heat sink connected to ground plane of the package is discussed. It is found that, for excellent near-field noise suppression effects, the heat sink must be connected to the ground plane.