Source abstract
Abstract
This article proposes a novel fast analytical method for full chip thermal analysis with reduction from 3-D to 2-D using the effective thermal characteristic length, called stepwise integration separation of variables (SISOV). Unlike the traditional separation of variables (SOV) method, which relies heavily on numerical approximation integration for Fourier series coefficient calculation, the proposed SISOV employs analytical stepwise integration by leveraging the uniform power densities across each block. This analytical technique mitigates discretization errors typically encountered in numerical integration, enhancing the accuracy. To overcome the inefficiencies inherent in the plain SOV method, we propose an adaptive rectangular mesh strategy to discretize the chip. This approach markedly reduces the number of required meshed blocks compared to grid sampling points, leading to a more efficient calculation of coefficients. Finally, the fast SISOV method is applied in the thermal uncertainty quantification (UQ) analysis of the full chip. The numerical results show that the proposed SISOV outperforms the plain SOV method, providing a speedup ranging from 2 to 63 times. Moreover, its accuracy surpasses that of the SOV method, with a mean absolute error (MAE) of just 0.05 K, indicating a substantial improvement. The thermal conductivity UQ analysis reveals that the SISOV method and the plain SOV method can achieve $26\times $ and $9\times $ faster performance compared to COMSOL, respectively.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Low-power high-performance VLSI design · Probabilistic and Robust Engineering Design · Advancements in Semiconductor Devices and Circuit Design
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
School of Microelectronics, Shanghai University, Shanghai, China
Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, China
State Key Laboratory of Radio Frequency Heterogeneous Integration, Shanghai Jiao Tong University, Shanghai, China
Funding
Joint Foundation of Key Laboratory of Shanghai Jiao Tong University-Xidian University, Ministry of Education · National Key Research and Development Program of China · National Natural Science Foundation of China · Shanghai Science and Technology Innovation Action
References (33)
Show source-provided references
11. Chiplet placement for 2.5D IC with sequence pair based tree and thermal consideration
33. Toward an open-source digital flow: First learnings from the OpenROAD project