Underfill Flow Void Solutions Through Process and Materials Interaction
Source abstract
Abstract
Silicon dies were thinned down and bump pitch became smaller to have a lot of input/output in electronic device packages especially in package on package configuration. This presents challenges on underfill (UF) dispense processing. UF voids occurred near the dispense side of bumps in multiple dispense pass technology. In this paper, we will review UF flow behavior on thin die technology, as well as the process and material interaction that cause UF void formation. Process optimization, such as the time between two dispense passes has become a critical parameter to eliminate UF voids without causing UF epoxy roll up that can cause reliability failure.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Electronic Packaging and Soldering Technologies · 3D IC and TSV technologies · VLSI and Analog Circuit Testing
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (5)
Show source-provided references
1. 10.1007/978-3-642-01273-010.1007/978-3-642-01273-0 ↗
2. The effect of flux residue and substrate wettability on underfill flow process in flip chip packages
3. 10.1109/EPTC.1998.75598010.1109/EPTC.1998.755980 ↗
4. The Next Step in Assembly and Packaging System Level Integration in the package (SiP) SiP White Paper V9 0 · 0
5. 10.1109/EPTC.2007.446968310.1109/EPTC.2007.4469683 ↗