Temperature effect on RF/analog and linearity parameters in DMG FinFET
Source abstract
Abstract
We systemically investigated the impact of variation in temperature on electrical parameters for a dual material gate (DMG) FinFET. We have highlighted the DC performance such as drain current characteristics, subthreshold swing (SS), and Ion/Ioff for the variation in temperature from 200 to 350 K. Furthermore, the influence of temperature on RF/Analog parameters like transconductance (gm), output conductance (gd), gate capacitance (CGG), intrinsic delay, transconductance generation factor (TGF = gm/ID), intrinsic gain (gm/gd), cutoff frequency (ft), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) are presented through TCAD simulator. We also discussed the influence of temperature on linearity parameters like gm2, gm3, VIP2, VIP3, IMD3, IIP3, and 1-dB compression point. A comparative study between DMG and single material gate (SMG) FinFET is also investigated.
Source: openaire · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (33)
Show source-provided references
1. K. Roy, S. Mukhopadhyay, H.M. Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE, 91(2), 305–327 (2003)10.1109/JPROC.2002.808156 ↗
2. D. Bhattacharya, N.K. Jha, FinFETs: from devices to architectures. Adv. Electr. (2014). https://doi.org/10.1155/2014/36568910.1155/2014/365689 ↗
3. S. Tang, L. Chang, N. Lindert et al., FinFET—a quasiplanar double-gate MOSFET. Proc. Int. Solid-State Circuits Confer. (2001). https://doi.org/10.1109/ISSCC.2001.91256810.1109/ISSCC.2001.912568 ↗
4. M.J. Kumar, A. Chaudhry, Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron Devices 51(4), 569–574 (2004)10.1109/TED.2004.823803 ↗
5. C. Li, Y. Zhuang, L. Zhang, Simulation study on FinFET with tri-material gate. 2012 IEEE international conference on electron devices and solid state circuit (EDSSC), Bangkok (2012). https://doi.org/10.1109/EDSSC.2012.648280210.1109/EDSSC.2012.6482802 ↗
6. R. Saha, S. Baishya, B. Bhowmick, 3D analytical modeling of surface potential, threshold voltage, and subthreshold swing in dual material Gate (DMG) SOI FinFET. J. Comput. Electron. 17, 153–162 (2018)10.1007/s10825-017-1072-x ↗
7. V. Narendar, S. Rai, S. Tiwari, A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET. J. Comput. Electron. 15, 1316–1325 (2016)10.1007/s10825-016-0899-x ↗
8. S. Saurabh, M.J. Kumar, Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans. Electron Devices 58(2), 404–441 (2011)10.1109/TED.2010.2093142 ↗
9. H. Lou et al., A junctionless nanowire transistor with a Dual Material Gate. IEEE Trans. Electron Devices 59(7), 1829–1836 (2012)10.1109/TED.2012.2192499 ↗
10. A. Kranti, G.A. Armstrong, Comparative analysis of nanoscale MOS device architectures for RF applications. Semicond. Sci. Technol. 22, 481 (2007)10.1088/0268-1242/22/5/005 ↗
11. J.P. Raskin, T.M. Chung, V. Kilchytska, D. Lederer, D. Flandre, Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization. IEEE Trans. Electron Devices 53(5), 1088–1095 (2006)10.1109/TED.2006.871876 ↗
12. D. Sharma, S.K. Vishvakarma, Analyses of DC and analog/RF performances for short channel quadruple-gate gateall-around MOSFET. Microelectron. J. 46, 731–739 (2015)10.1016/j.mejo.2015.05.008 ↗
13. B. Parvais et al., FinFET technology for analog and RF circuits. 2007 14th IEEE International conference on electronics, circuits and systems, Marrakech (2007). https://doi.org/10.1109/ICECS.2007.451096010.1109/ICECS.2007.4510960 ↗
14. D. Lederer et al., Dependence of FinFET RF performance on fin width. Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, CA (2006). https://doi.org/10.1109/SMIC.2005.158788710.1109/SMIC.2005.1587887 ↗
15. A. Kumar, Analog and RF performance of a multigate FinFET at nano scale. Superlattices Microstruct. 100, 1073–1080 (2016)10.1016/j.spmi.2016.10.073 ↗
16. R.K. Sharma, C.A. Dimitriadis, M. Bucher, A comprehensive analysis of nanoscale single- and multi-gate MOSFETs. Microelectron. J. 52, 66–72 (2016)10.1016/j.mejo.2016.03.004 ↗
17. S.K. Mohapatra, K.P. Pradhan, P.K. Sahu, Temperature dependence inflection point in ultra-thin Si directly on Insulator (SDOI) MOSFETs: an influence to key performance metrics. Superlattices Microstruct 78, 134–143 (2015)10.1016/j.spmi.2014.11.037 ↗
18. Y. Hashim, Temperature effect on ON/OFF current ratio of FinFET transistor. 2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), Batu Ferringhi, Penang (2017). https://doi.org/10.1109/RSM.2017.806916010.1109/RSM.2017.8069160 ↗
19. A. Diab, G.A. Torres Sevilla, S. Cristoloveanu, M.M. Hussain, Room to high temperature measurements of flexible SOI finfets with sub-20-nm fins. IEEE Trans. Electron Devices 61(12), 3978–3984 (2014)10.1109/TED.2014.2360659 ↗
20. R.R. Das, S. Maity, D. Muchahary, C.T. Bhunia, Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material. Superlattices Microstruct. 103, 262–269 (2017)10.1016/j.spmi.2017.01.041 ↗
21. R. Saha, B. Bhowmick, S. Baishya, Effects of temperature on electrical parameters in GaAs SOI FinFET and application as digital inverter. 2017 Devices for Integrated Circuit (DevIC), Kalyani (2017). https://doi.org/10.1109/DEVIC.2017.807399210.1109/DEVIC.2017.8073992 ↗
22. R. Das, S. Baishya, Investigation on effect of temperature on dual gate material gate/drain underlap germanium FinFET. J. Nanoelectr. Optoelectr. 13(7), 980–985 (2018)10.1166/jno.2018.2339 ↗
23. Sentaurus Device User Guide (Synopsys, Inc., Mountain View, CA 2011)
24. R. Rios et al., Comparison of junctionless and conventional trigate transistors with Lg down to 26 nm. IEEE Electron Device Lett. 32(9), 1170–1172 (2011)10.1109/LED.2011.2158978 ↗
25. S. Rai, J.S.,Wanjul Dattatray, R.A.Mishra,S. Tiwari, Modelling, design, and performance comparison of triple gate cylindrical and partially cylindrical FinFETs for low-power applications. International Scholarly Research Network, ISRN Electronics (2012). https://doi.org/10.5402/2012/82745210.5402/2012/827452 ↗
26. A. Kranti, G.A. Armstrong, Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans. Circuits Syst. I Regul. Pap. 57(12), 3048–3054 (2010)10.1109/TCSI.2010.2071470 ↗
27. A.O. Adan, T. Yoshimasu, S. Shitara, N. Tanba, M. Fukurni, Linearity and low-noise performance of SOI MOSFETs for RF applications. IEEE Trans. Electron Devices 49(5), 881–888 (2002)10.1109/16.998598 ↗
28. W. Ma, S. Kaya, A. Asenov, Study of RF linearity in sub-50 nm MOSFETs using simulations. J. Comput. Electron. 2, 347–352 (2003)10.1023/B:JCEL.0000011450.37111.9d ↗
29. S.P. Kumar, A. Agrawal, R. Chaujar, R.S. Gupta, M. Gupta, Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab. 51, 587–596 (2011)10.1016/j.microrel.2010.09.033 ↗
30. P. Ghosh, S. Haldar, R.S. Gupta, M. Gupta, An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans. Electron Devices 59(12), 3263–3268 (2012)10.1109/TED.2012.2219537 ↗
31. B. Razavi, RF microelectronics. (Prentice Hall; Princeton, 1998)
32. H. Jiang et al., Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs. Semicond. Sci. Technol. 29, 115021 7 (2014). https://doi.org/10.1088/0268-1242/29/11/11502110.1088/0268-1242/29/11/115021 ↗
33. G. C. Tettamanzi, A. Paul, S. Lee, Gerhard Klimeck, S. Rogge, New Tools for the Direct Characterisation of FinFETS (2013) Birck and NCN Publications. Paper 1310. https://doi.org/10.4032/978981436403410.4032/9789814364034 ↗