Source abstract
Abstract
Abstract The mass production of µLEDs requires an upscaling approach on 200 mm wafers, which implies the deployment of a technology that achieves zero defectivity without liftoff. In this report, Nanoimprint lithography (NIL) processing is successfully optimized for nanostructuring GaN‐based Silicon‐On‐Insulator (SOI) substrates. The etching of SiO2/GaN/AlN/Si/SiO2 layers using different plasmas is conducted and multi‐layer nanopillars 100–200 mm in diameter are fabricated. This approach generates zero‐defect arrays of pillars, which is particularly advantageous for the growth process. In addition, the SiO2 at the bottom of the pillar allows it to twist during the subsequent GaN regrowth, as this layer becomes soft at the growth temperature >1000 °C. This ability to deform enables a coalescence of pillars into layers with reduced dislocation density. As a result, high‐quality GaN microplatelets and µLEDs are grown via a bottom‐up approach based on pendeoepitaxy using metal–organic vapor phase epitaxy (MOVPE). The fabricated µLEDs have a very smooth surface with a roughness of 0.6 nm which facilitated the implementation of an easy and simple transfer protocol. Adhesive tape and metalmetal bonding, are used to bond the µLEDs onto a metal‐coated silicon substrate. The reported findings offer exciting new insights into the development of high‐performance displays.
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Research context
OpenAlex topics: GaN-based semiconductor devices and materials · ZnO doping and properties · Nanowire Synthesis and Applications
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
CNRS CEA/LETI‐Minatec Grenoble INP LTM Université Grenoble Alpes 17 Rue des Martyrs Grenoble 38054 France
CEA‐LETI Université Grenoble Alpes 17 Rue des Martyrs Grenoble 38054 France
CRHEA‐CNRS Université Cote d'Azur Rue Bernard Gregory Valbonne 06560 France
Centre de mise en forme des matériaux (CEMEF) CNRS MINES Paris PSL Univ. CS 10207 rue Claude Daunesse Sophia Antipolis 06904 France
MajuLab, International Research Laboratory IRL 3654 CNRS Université Cote d'Azur Sorbonne Université National University of Singapore Nanyang Technological University Singapore 38054 Singapore
References (30)
Show source-provided references
30. K. S.Choi J.Joo Y. S.Eom G. M.Choi K. S.Jang C.Lee J. W.Choi 71st Electronic Components and Technology Conf. (ECTC). IEEE2021 pp.1607–1613.
10.1109/ECTC32696.2021.00255 ↗