A New Printed Electronics Approach Eliminating Redundant Fabrication Process of Vertical Interconnect Accesses: Building Multilayered Circuits in Porous Materials

Abstract Printed electronics are striving for smaller size, increased functionality, and lower energy consumption, which impose critical demand for multilayered printed circuits. As a low‐cost and green substrate, cellulose paper has become the most attractive choice for the printing of sustainable and disposable electronics. However, the redundant processes of drilling holes and/or depositing of dielectric materials, when fabricating the vertical interconnect access (VIA) for these multilayered circuits, greatly increase the cost. In this paper, a simple, cost‐effective, and scalable method is proposed for fabricating high‐performance, multilayered paper‐based circuits which contain highly conductive VIAs without physically drilling holes or depositing additional dielectric material. Taking advantages of inkjet printing and electroless copper deposition, the metallization depth of the substrate can be controlled with ease. In the proposed method, the porous structure of cellulose paper, which is previously an obstacle to printed electronics, becomes an advantage by triggering the 3D copper deposition, resulting in an ultralow sheet resistance of ≈4.8 mΩ sq⁻¹ for single layer traces and ≈2.6 mΩ sq⁻¹ for VIAs. A functional double‐layered and battery‐free device with drill‐less VIA, featuring an energy harvesting function, is fabricated using the proposed method on paper for the first time.