Influence of Pt Nanoparticle Induced Defects and Surface Coverage in Determining Asymmetric Programming/Erasing Signatures for Nanocrystal Embedded Nonvolatile Memory Applications

Metal nanocrystal embedded nonvolatile memory (NVM) devices have attracted significant attention over the past two decades as promising alternatives to conventional floating gate memory devices. This study explores the applicability of sub‐2 nm Pt nanoparticle (NP) embedded in ALD Al₂O₃ as charge storage nodes in Si‐based NVM devices. The influence of Pt NP‐induced border traps within Al₂O₃ near the Si surface and their surface coverage dependent pinning of Pt NP work function are explored as part of this study. The pinning of the nanocrystal memories induced by a high density of dangling bonds near the Pt NP/Al₂O₃ interface skews the expected charging/discharging characteristics with electron programming favored over holes. The degree of this pinning has been probed utilizing C–V measurements and has been dependent on the density of Al₂O₃ dangling bonds near the Pt NP surface. This density of dangling bonds acting as border traps has been observed as an increasing function of the Pt NP surface percent coverage. Gaining adequate understanding the location, energy, and positioning of the energy levels of these defects at the metal/high‐k interface relative to Si band gap can help overcome poor retention and leakage issues that typically compromise the performance of new generation memory devices.