journal article·2022-08-01

Comparative Analysis of Crosstalk Effects in Dielectric Inserted Horizontal andVertical Multi-layer GNR Interconnects for Ternary Logic System

Gurijala Deepthi, Madhavi Tatineni

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Abstract

In this work, the performance of copper (Cu), dielectric inserted horizontal graphene nanoribbon (Di-HGNR) interconnect and dielectric inserted vertical graphene nanoribbon (Di-VGNR) interconnects are investigated using active shielding and passive shielding techniques. However, the analysis is carried out by adapting driver-interconnect-load system. This analysis considers the interconnect length from 500 to 2000 μ m for 10 nm technology node. Further, the crosstalk induced effects on various interconnect structures are examined. It is envisaged that Di-VGNR exhibits lowest propagation delay compared to Cu and Di-HGNR. Further, the in-phase and out-phase crosstalk delay among the coupled interconnect lines is determined. It is investigated that active shielded Di-VGNR has least crosstalk induced delay compared to other interconnect structures considered in this study. Therefore, Di-VGNR interconnects outperforms Cu and Di-HGNR and are best suited for future VLSI interconnects.
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Research context

OpenAlex topics: Graphene research and applications · Copper Interconnects and Reliability · Low-power high-performance VLSI design

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References (34)

Show source-provided references
1. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits10.1109/92.831439 ↗
2. Rabaey · 2003
3. An analytical approach to dynamic crosstalk in coupled interconnects10.1016/j.mejo.2009.12.011 ↗
4. Alteration of Cu conductivity in the size effect regime10.1116/1.1642639 ↗
5. ‘Influence of surface and grain-boundary scattering on the resistivity of copper in reduced dimensions10.1063/1.1703844 ↗
6. Modeling of crosstalk effects in multiwall carbon nanotube interconnects10.1109/TEMC.2011.2172982 ↗
7. Modeling, analysis, and design of graphene nano-ribbon interconnects10.1109/TED.2009.2024254 ↗
8. Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects10.1016/j.vlsi.2021.05.004 ↗
9. Signal transmission analysis of multilayer graphenenano-ribbon (MLGNR) interconnects10.1109/TEMC.2011.2172947 ↗
10. Graphene based on-chip interconnects and TSVs: prospects and challenges10.1109/MNANO.2014.2355275 ↗
11. Stability and delay analysis of multi-layered GNR and multi-walled CNT interconnects10.1007/s10825-015-0691-3 ↗
12. A novel unified model for copper and MLGNR Interconnects using voltage- and current-mode signalling schemes10.1109/TEMC.2016.2587821 ↗
13. Performance modelling for single- and multiwall carbon nanotubes as signal and power interconnects in gigascale systems10.1109/TED.2008.2003028 ↗
14. Carbon nanomaterials for next-generation interconnects and passives: Physics, status, and prospects10.1109/TED.2009.2026524 ↗
15. The electronic properties of graphene10.1103/RevModPhys.81.109 ↗
16. Performance improvement in SC-MLGNRs interconnects using interlayer dielectric insertion10.1109/TETC.2015.2486748 ↗
17. Modelling and performance analysis of dielectric inserted side contact multilayer graphenenanoribbon interconnects10.1049/iet-cds.2016.0376 ↗
18. Vertical graphene nanoribbion interconnects at the end of the roadmap10.1109/TED.2018.2822664 ↗
19. Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach10.1016/j.mejo.2015.09.018 ↗
20. Mouftah · Implementation of 3- valued logic with c.o.s.m.o.s. integrated circuits · 1974 · 10 · 44110.1049/el:19740350 ↗
21. Design of a ternary memory cell using CNTFETs10.1109/TNANO.2012.2211614 ↗
22. Performance optimization of critical nets through active shielding10.1109/TCSI.2004.838247 ↗
23. Analysis of crosstalk effects for multiwalled carbon nanotube bundle interconnects in ternary logic and comparison with cu interconnects10.1109/TNANO.2016.2633460 ↗
24. A Comparative performance analysis of copper and MWCNT bundle interconnects in ternary logic10.1109/ICEE.2018.8472569 ↗
25. Efficient passive shielding of MWCNT interconnects to reduce crosstalk effects in multiple valued logic circuits10.1109/TEMC.2018.2863378 ↗
26. Active shielding of MWCNT bundle interconnects: an efficient approach to cancellation of crosstalk-induced functional failures in ternary logic10.1109/TEMC.2017.2788500 ↗
27. Comparative analysis of the crosstalk effects in multilayer graphene nanoribbon and MWCNT interconnects in sub-10 nm technologies10.1109/TEMC.2019.2903567 ↗
28. Design of MWCNT based Through Silicon Vias with Polymer Liners to Reduce the Crosstalk Effects10.1149/2162-8777/ab80b4 ↗
29. Evaluation and reduction of signal integrity issues in mutliwalled carbon nanotube on-chip VLSI interconnects10.1149/2162-8777/ac1c5b ↗
30. CNTFET-based design of ternary logic gates and arithmetic circuits10.1109/TNANO.2009.2036845 ↗
31. A new method on designing and simulating CNTFET based ternary gates and arithmetic circuits10.1016/j.mejo.2017.02.018 ↗
32. Novel CNFET ternary circuit techniques for high-performance and energy efficient design10.1049/iet-cds.2018.5036 ↗
33. High-performance and energy-efficient NFET-based designs for ternary logic circuits10.1109/ACCESS.2019.2928251 ↗
34. Quality of signal improvement in prominent CNTFET based ternary logic system for futuristic dielectric inserted MLGNRs for integrated circuit designs10.1149/2162-8777/ac5a71 ↗