Heat Transport at Silicon Grain Boundaries

Abstract Engineering microstructural defects, like grain boundaries, offers superior control over transport properties in energy materials. However, technological advancement requires establishing microstructure‐property relations at the micron or finer scales, where most of these defects operate. Here, the first experimental evidence of thermal resistance for individual silicon grain boundaries, estimated with a Gibbs excess approach, is provided. Coincident site lattice boundaries exhibit uniform excess thermal resistance along the same boundary, but notable variations from one boundary to another. Boundaries associated with low interface energy generally exhibit lower resistances, aligning with theoretical expectations and previous simulations, but several exceptions are observed. Transmission electron microscopy reveals that factors like interface roughness and presence of nanotwinning can significantly alter the observed resistance, which ranges from ∼0 to up to ∼2.3 m²K/GW. In stark contrast, significantly larger and less uniform values ‐ from 5 to 30 m²K/GW ‐ are found for high‐angle boundaries in spark‐plasma‐sintered polycrystalline silicon. Further, finite element analysis suggests that boundary planes that strongly deviate from the sample vertical (beyond ∼45°) can show up to 3‐times larger excess resistance. Direct correlations of properties with individual defects enable the design of materials with superior thermal performance for applications in energy harvesting and heat management.