journal article·2021-03-07Open access

High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs

Mu-Chun Wang, Wen-Ching Hsieh, Chii-Ruey Lin, Wei-Lun Chu, Wen-Shiang Liao, Wen-How Lan

Crystals· Volume 11· Issue 3

Abstract

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio have been developed after integrating a 14Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. Under the lower gate voltage (VGS-VT) and the higher drain/source voltage VDS, the channel-length modulation (CLM) effect coming from the interaction impact of vertical gate field and horizontal drain field was increased and had to be revised well as the channel length L was decreased. Compared to the 28-nm MOSFETs, the interaction effect from the previous at the tested FinFETs on SOI substrate with the short-channel length L is lower than that at the 28-nm device, which means the interaction severity of both fields for nFinFETs is mitigated, but still necessary to be concerned.
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Research context

OpenAlex topics: Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Integrated Circuits and Semiconductor Failure Analysis

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Department of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu 30401, Taiwan

Department of Electro-Optical Engineering, Minghsin University of Science and Technology, Hsinchu 30401, Taiwan

Department of Mechanical Engineering, National Taipei University of Technology, Taipei 10608, Taiwan

Department of Mechanical Engineering, Minghsin University of Science and Technology, Hsinchu 30401, Taiwan

Department of Electrical Engineering, National University of Kaohsiung, Kaohsiung 81148, Taiwan

References (58)

Show source-provided references
1. Xiao, H. (2012). Introduction to Semiconductor Manufacturing Technology, SPIE. [2nd ed.].10.1117/3.924283 ↗
2. Dosi, G. (1984). Technical Change and Industrial Transformation: The theory and an Application to Semiconductor Industry, Macmillan Press. [1st ed.].10.1007/978-1-349-17521-5_3 ↗
3. Baldauf, T., Wei, A., Illgen, R., Flachowsky, S., Herrmann, T., Höntschel, J., Horstmann, M., Klix, W., and Stenzel, R. (2011, January 7–9). Study of 22/20 nm trigate transistors compatible in a low-cost hybrid FinFET/planar CMOS process. Proceedings of the IEEE ISDRS, College Park, MD, USA.10.1109/ISDRS.2011.6135350 ↗
4. Pham, D., Larson, L., and Yang, J. (2006, January 15–16). FinFET device junction formation challenges. Proceedings of the IEEE IWJT, Shanghai, China.10.1109/IWJT.2006.220864 ↗
5. LaPedus, M. (2021, January 03). Transistor Options beyond 3 nm. Semicond. Eng., Feb. Available online: https://semiengineering.com/transistor-options-beyond-3nm/.
6. Vidya, S., Kamat, S., Khan, A., and Venkatesh, V. (2018, January 1–3). 3D FinFET for next generation nano devices. Proceedings of the IEEE ICCTCT, Coimbatore, Tamil Nadu, India.10.1109/ICCTCT.2018.8550967 ↗
7. Challenges and limitations of CMOS scaling for FinFET and beyond architectures10.1109/TNANO.2019.2942456 ↗
8. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm10.1109/16.887014 ↗
9. Wong, H.S.P., Chan, K.K., and Taur, Y. (1997, January 10). Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel. Proceedings of the IEEE IEDM, Washington, DC, USA.
10. Heavy-ion-induced current transients in bulk and SOI FinFETs10.1109/TNS.2012.2221478 ↗
11. Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs10.1109/TED.2007.908908 ↗
12. Device and circuit performance estimation of junctionless bulk FinFETs10.1109/TED.2013.2256137 ↗
13. Mittl, S., and Guarín, F. (2015, January 19–23). Self-heating and its implications on hot carrier reliability evaluations. Proceedings of the IEEE IRPS, Monterey, CA, USA.10.1109/IRPS.2015.7112726 ↗
14. Poljak, M., Jovanovic, V., and Suligoj, T. (2008, January 5–7). SOI vs. bulk FinFET: Body doping and corner effects influence on device characteristics. Proceedings of the IEEE MELECON, Ajaccio, France.10.1109/MELCON.2008.4618472 ↗
15. Comparison of electrical characteristics between bulk MOSFET and silicon-on-insulator (SOI) MOSFET
16. Krivec, S., Prgić, H., Poljak, M., and Suligoj, T. (2014, January 26–30). Comparison of RF performance between 20 nm-gate bulk and SOI FinFET. Proceedings of the IEEE MIPRO, Opatija, Croatia.10.1109/MIPRO.2014.6859530 ↗
17. Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: Optimization of the device architecture10.1016/S0038-1101(01)00111-3 ↗
18. Silicon on insulator technologies and devices: From present to future10.1016/S0038-1101(00)00271-9 ↗
19. Deshmukh, R., Khanzode, A., Kakde, S., and Shah, N. (2015, January 10–12). Compairing FinFETs: SOI vs. Bulk: Process variability, process cost, and device performance. Proceedings of the IEEE IC4, Indore, India.10.1109/IC4.2015.7375645 ↗
20. Godara, M., Madhu, C., and Joshi, G. (2018, January 24–25). Comparison of electrical characteristics of 28 nm bulk MOSFET and FDSOI MOSFET. Proceedings of the IEEE EDKCON, Kolkata, India.10.1109/EDKCON.2018.8770413 ↗
21. FinFET analogue characterization from DC to 110 GHz10.1016/j.sse.2005.07.011 ↗
22. Purely analytical extraction of an improved nonlinear FinFET model including non-quasi-static effects10.1016/j.mee.2009.04.006 ↗
23. High-frequency noise performance of 60-nm gate-length FinFETs10.1109/TED.2008.2003097 ↗
24. Microwave noise modeling of FinFETs10.1016/j.sse.2010.10.010 ↗
25. Neamen, D.A. (2006). An Introduction to Semiconductor Devices, McGraw-Hill. [1st ed.].
26. Modification of Early effect for 28-nm nMOSFETs deposited with HfZrOx dielectric after DPN process accompanying nitrogen concentrations10.1109/TPS.2014.2357024 ↗
27. Yang, H.C., Du, C.K., Liao, W.S., Jhang, J.Z., Lee, Y.H., Chen, T.Y., Liao, K.F., Wang, M.C., Chi, S., and Wang, S.J. (2013, January 2–4). The side effects on n-type FinFET device. Proceedings of the IEEE INEC, Singapore.10.1109/INEC.2013.6466084 ↗
28. Streetman, B.G. (2016). , Banerjee, S.K. Solid State Electronic Devices, Pearson. [7th ed.].
29. Hu, C. (2010). Modern Semiconductor Devices for Integrated Circuits, Pearson. [1st ed.].
30. Shang, H., Chang, L., Wang, X., Rooks, M., Zhang, Y., To, B., Babich, K., Totir, G., Sun, Y., and Kiewra, E. (2006, January 13–15). Investigation of FinFET devices for 32 nm technologies and beyond. Proceedings of the IEEE VLSIT, Honolulu, HI, USA.
31. Wangm, X., Bryantm, A., Dokumacim, O., Oldigesm, P., and Haenschm, W. (2007). Simulation study of multiple fin FinFET design for 32 nm technology node and beyond. Simulation of Semiconductor Processes and Devices 2007, Springer.10.1007/978-3-211-72861-1_30 ↗
32. Avushyan, S., Petrosyan, K., Kaplanyan, T., Shaljyan, D., Mikaelyan, L., Shukhyan, N., and Momjyan, A. (2019, January 16–18). Current scaling of multi-fin devices in FinFET process. Proceedings of the IEEE ELNANO, Kyiv, Ukraine.10.1109/ELNANO.2019.8783896 ↗
33. The impact of fin number on device performance and reliability for multi-fin tri-gate n- and p-type FinFET10.1109/TDMR.2018.2866800 ↗
34. Wang, F., Xie, Y., Bernstein, K., and Luo, Y. (2006, January 2–3). Dependability analysis of nano-scale FinFET circuits. Proceedings of the IEEE ISVLSI, Karlsruhe, Germany.
35. Lu, D., Dunga, M., Niknejad, A., Hu, C., Liang, F., Hung, W., Lee, J., Hsu, C., and Chiang, M. (2018, January 2–4). Compact device models for FinFET and beyond. Proceedings of the AWAD, Kitakyushu, Japan. Available online: http://arXiv:2005.02580.
36. Chauhan, Y., Lu, D., Vanugopalan, S., Khandelwal, S., Duarte, J., Paydavosi, N., Niknejad, A., and Hu, C. (2015). FinFET Modeling for IC Simulation and Design, Academic Press. [1st ed.].
37. Kim, S., Kim, J., Jang, D., Ritzenthaler, R., Parvais, B., Mitard, J., Mertens, H., Chiarella, T., Horiguchi, N., and Lee, J. (2020). Comparison of temperature dependent carrier transport in FinFET and gate-all-around nanowire FET. Appl. Sci., 10.10.3390/app10082979 ↗
38. Khan, T.E.A., Sheena, S., and Hameed, T.A.S. (2018, January 11–13). An investigation on the effect of LER on threshold voltage and On Current of SOI, bulk and GAA FinFETs. Proceedings of the IEEE ICETIETR, Ernakulam, India.10.1109/ICETIETR.2018.8529135 ↗
39. Liao, W.S. (2006, January 14). A high aspect ratio Si-fin FinFET fabricated with 193 nm scanner photolithography and thermal oxide hard mask etching techniques. Proceedings of the SPIE 6156, San Jose, CA, USA.10.1117/12.659648 ↗
40. Investigation of reliability characteristics in NMOS and PMOS FinFETs10.1109/LED.2008.2000723 ↗
41. A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer10.1016/j.sse.2016.09.017 ↗
42. Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs10.1109/LED.2006.875721 ↗
43. Elgomati, H.A., Majlis, B.Y., Salehuddin, F., Ahmad, I., Zaharim, A., and Hamid, F.A. (2011, January 28–30). Cobalt silicide and titanium silicide effects on nano devices. Proceedings of the IEEE RSM, Kota Kinabalu, Malaysia.10.1109/RSM.2011.6088344 ↗
44. Stressor SiNx contact etch stop layer (CESL) technology and its application in nano-scale transistors
45. Strain-engineering in nanowire field-effect transistors at 3 nm technology node10.1016/j.physe.2020.113964 ↗
46. Voisin, S., Knopik, V., Forest, J., and Kerhervé, E. (2021, January 10–15). A 65 nm CMOS SOI 4-bit digitally controlled variable gain amplifier for Ka-band beamforming. Proceedings of the IEEE EuMIC, Utrecht, Netherlands.
47. Shauly, E.N. (2018). Physical, electrical, and reliability considerations for copper BEOL layout design rules. J. Low Power Electron. Appl., 8.10.3390/jlpea8020020 ↗
48. The effect of quantum confinement and discrete dopants in nanoscale 50 nm nMOSFETs: A three-dimensional simulation10.1088/0957-4484/13/3/311 ↗
49. Schulz, T., Xiong, W., Cleavelin, C.R., Schruefer, K., Gostkowski, M., Matthews, K., Gebara, G., Zaman, R.J., Patruno, P., and Chaudhry, A. (2005, January 3–6). Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs). Proceedings of the IEEE SOI, Honolulu, HI, USA.
50. A Si-based bulk FinFET by novel etching process with mask-less and photoresist-free lithography technique10.1504/IJNT.2015.066196 ↗
51. Dry etching process for bulk FinFET manufacturing10.1016/j.mee.2008.10.001 ↗
52. Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs10.1109/TED.2015.2436351 ↗
53. Performance and device design based on geometry and process considerations for 14/16-nm Strained FinFETs10.1109/TED.2016.2520583 ↗
54. Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14 nm node FinFETs10.1016/j.sse.2016.07.024 ↗
55. Curing of hot-carrier induced damage by gate-induced drain leakage current in gate-all-around FETs10.1109/LED.2019.2946393 ↗
56. Efficient temperature sensor based on SOI gate-all-around electrostatically formed nanowire transistor10.1109/TED.2019.2919389 ↗
57. Nitride induced stress affecting crystallinity of sidewall damascene gate-all-around nanowire poly-Si FETs10.1109/TNANO.2020.2981394 ↗
58. Seon, Y., Chang, J., Yoo, C., and Jeon, J. (2021). Device and circuit exploration of multi-nanosheet transistor for sub-3 nm technology node. Electronics, 10.10.3390/electronics10020180 ↗