High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking

Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay.Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process.Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters.In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain.Void-free vias 70 m deep and 10 m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment.The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu͑I͒ thiolate accelerant.