article·2003-01-01Open access

High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking

Jian‐Jun Sun, Kazuo Kondo, Takuji Okamura, Seung Jin Oh, M. Tomisaka, H. Yonemura, M. Hoshino, Kenji Takahashi

Abstract

Through-chip electrodes with high aspect ratios can offer the shortest interconnection and reduce signal delay. Copper has been selected as that electrode material because of its good compatibility to conventional multilayer interconnection in large-scale integration and back end-of-line processes. In this paper, filling vias with higher aspect ratio, 10 μm 2 and 70 μm depth, used for through-chip electrodes is reported. Removing overhang at via tops is important to achieve perfect via filling. Upon testing a series of electrodeposition conditions, conformal electrodeposits were obtained. With those conformal electrodeposits, seams and voids always remained at the via center. Perfect via filling was achieved by the pulse reverse plating method and by increasing Janus Green B concentration up to 20 mg/L in the plating bath. © 2003 The Electrochemical Society. All rights reserved.
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Research context

OpenAlex topics: Electrodeposition and Electroless Coatings · Corrosion Behavior and Inhibition · Electronic Packaging and Soldering Technologies

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