Sensitivity analysis of junctionless silicon NT-TFET and performance metrics comparison with the silicon NT-TFET
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OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Semiconductor materials and devices · Integrated Circuits and Semiconductor Failure Analysis
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References (25)
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1. Duvvury C (1986) A guide to short-channel effects in MOSFETs. IEEE Circuits Devices Mag 2(6):6–1010.1109/MCD.1986.6311897 ↗
2. Huguenin JL, Bidal G, Denorme S, Fleury D, Loubet N, Pouydebasque A, Perreau P et al (2010) Gate-all-around technology: taking advantage of ballistic transport. Solid State Electron 54(9):883–88910.1016/j.sse.2010.04.029 ↗
3. Nagy D, Indalecio G, Garca Loureiro AJ, Elmessary MA, Kalna K, Seoane N (2018) FinFET versus gate-all-around nanowire FET: performance, scaling and variability. IEEE J Electron Devices Soc 6:332–34010.1109/JEDS.2018.2804383 ↗
4. Xie H, Liu H (2023) Performance assessment of a junctionless heterostructure tunnel FET biosensor using dual material gate. Micromachines 14:80510.3390/mi14040805 ↗
5. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'neill B, Blake A, White M, Kelleher AM, McCarthy BP, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–910.1038/nnano.2010.15 ↗
6. Fallahnejad M, Amini A, Khodabakhsh A, Vadizadeh M (2021) High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters. Applied Physics A 128: n. pag10.1007/s00339-021-05153-w ↗
7. Baruah RK, Paily RP (2013) A dual material double-layer gate stack junctionless transistor for enhanced analog performance. In: Gaur MS, Zwolinski M, Laxmi V, Boolchandani D, Sing V, Sing AD (eds) VLSI design and test. Communications in computer and information science, vol 382. Springer, Berlin, Heidelberg10.1007/978-3-642-42024-5_15 ↗
8. ChenL Cai F, Otunoyo U, Lu WD (2016) Vertical Ge/Si core shell nanowire junctionless transistors. Nanoletters 16(1):42–426
9. Parihar MS, Kranti A (2015Apr 10) Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications. Nanotechnology 26(14):14520110.1088/0957-4484/26/14/145201 ↗
10. Shreya S, Khan AH, Kumar N, Intekhab Amin S, Anand S (2020) core-shell junctionless nanotube tunnel field effect transistor: Design and sensitivity analysis for biosensing application. IEEE Sensors J 20:672–67910.1109/JSEN.2019.2944885 ↗
11. Tekleab D (2014) Device performance of silicon nanotube field effect transistor. IEEE Electron Device Lett 35(5):506–50810.1109/LED.2014.2310175 ↗
12. Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11(10):4393–439910.1021/nl202563s ↗
13. Ambika R, Srinivasan R (2016) Performance analysis of n-type junctionless silicon nanotube field effect transistor. J Nanoelectron Optoelectron 11:1–710.1166/jno.2016.1899 ↗
14. Scarlet SP, Vinodhkumar N, Srinivasan R (2021) Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering. J Comput Electron 20:209–21710.1007/s10825-020-01611-5 ↗
15. Gedam A, Acharya B, Mishra GP (2021) Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon 13:167–17810.1007/s12633-020-00410-8 ↗
16. Okte L, Raman A, Raj B et al (2022) Junctionless silicon nanotube tunnel field effect transistor based resistive temperature detector. Silicon 14:3281–329110.1007/s12633-021-01102-7 ↗
17. Ambika R, Keerthana N, Raj S (2017) Realization of silicon nanotube tunneling FET on junctionless structure using single and multiple gate workfunction. Solid-State Electron 127:45–5010.1016/j.sse.2016.10.037 ↗
18. Kumar N, Amin SI, Anand S (2020) Design and performance optimization of novel core–shell dopingless GAA-nanotube TFET with Si 0.5 Ge 0.5-based source. IEEE Trans Electron Devices 67(3):789–79510.1109/TED.2020.2965244 ↗
19. Fahad HM, Hussain MM (2013) High-performance silicon nanotube tunneling FET for ultralow-power logic applications. IEEE Trans Electron Devices 60(3):1034–103910.1109/TED.2013.2243151 ↗
20. Singh A, Chaudhury S, Pandey CK, Sharma SM, Sarkar CK (2019) Design and analysis of high k silicon nanotube tunnel FET device. IET Circuit Devices and Systems 13(8):1305–131010.1049/iet-cds.2019.0230 ↗
21. Singh A, Pandey CK, Nanda U (2022) Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction. Microelectron J 126:10551210.1016/j.mejo.2022.105512 ↗
22. Ambika R, Raj S (2017) Sensitivity of silicon nanotube field effect transistor to structural process parameters. J Nanoelectronics Optoelectronics 12:1098–110410.1166/jno.2017.2150 ↗
23. Ambika R, Raj S (2018) Impact of structural process variation on junctionless silicon nanotube FET. Adv Nat Sci: Nanosci Nanotechnology 9:035015
24. Rajendiran P, Nisha Justeena A (2023) Structural process variation on silicon nanotube tunnel field-effect transistor. Silicon 15:7149–715610.1007/s12633-023-02575-4 ↗
25. Synopsys Sentaurus TCAD Ver. J-2014.09, Synopsys, Inc., Mountain View, CA, USA. (2014) https://www.synopsys.com/home.aspx