Wafer-Scale Monolayer MoS ₂ with Tunable Grain Size via Grain Boundary Engineering for Neuromorphic Computing

Grain boundaries (GBs) in two-dimensional (2D) materials, once regarded as detrimental defects, are now increasingly recognized as functional features for tailoring material properties. Here, we report a grain-boundary engineering strategy based on a diameter-tunable chemical vapor deposition (DT-CVD) technique, enabling the wafer-scale growth of monolayer MoS 2 with controlled grain sizes. Systematic tuning of GB density is achieved by adjusting the inner quartz tube diameter while maintaining uniform monolayer morphology and crystallinity. Structural and spectroscopic characterizations confirm that increasing GB density introduces shallow energy barriers and band bending effects, which are exploited in memtransistor architectures to induce tunable analog switching. Simulations and electrical measurements show that grain-boundary-induced charge trapping and ionic migration synergistically govern the observed resistive switching behavior. Among all devices, the grain size-tunable MoS 2 memtransistor with an equivalent grain size of ∼114 ± 48 nm achieves an optimal trade-off between analog precision and cycling endurance. It supports 64-level conductance modulation along with robust long-term synaptic plasticity. When implemented in neural networks, it delivers high training and inference accuracy across diverse data sets, underscoring its promise for next-generation energy-efficient neuromorphic systems.