Low‐Voltage Driven High‐Speed and Low‐Energy Memory Operations by Novel TiTe ₂ /Sc _0.3 Sb ₂ Te ₃ Phase‐Change Heterostructure

Abstract Phase‐change memory (PCM) has long suffered from performance drawbacks such as slow Set speed, high Reset energy, and large multistate drift, severely impeding the developments of high‐capacity storage and high‐parallel computing chips. It is challenging to simultaneously improve these drawbacks to leading levels, especially when the low‐driving‐bias criterion must be met for developing PCM chips at advanced technological nodes below ≈16‐40 nm. Here, an innovative TiTe ₂ /Sc _0.3 Sb ₂ Te ₃ heterostructure is designed to address this issue. The resulting PCM cells demonstrated the lowest Reset energy (≈6.40 pJ bit ⁻¹ ), the fastest Set speed (≈4 ns) within the low‐voltage (< ≈2.5 V) regime, and the capability to reach sub‐ns Set speeds (≈0.6 ns) under higher driving bias, alongside the smallest multilevel resistance drift (≈10 ⁻⁴ –3 × 10 ⁻³ ), outperforming the relevant monolithic and existing heterostructured cells equipped with even smaller bottom electrodes. In situ electrical‐pulse driven microscopic observations unveiled the reversible two‐dimensional (2D), phase‐transition mechanisms underlying the comprehensively enhanced electrical performances of the TiTe ₂ /Sc _0.3 Sb ₂ Te ₃ heterostructure. The work thus offers valuable guidance for exploring novel chalcogenide heterostructures to achieve more superior PCM performances.