Show source-provided references
3. Jo, S. H.; Kumar, T.; Narayanan, S.; Lu, W. D.; Nazarian, H. 3D-Stackable Crossbar Resistive Memory Based on Field Assisted Superlinear Threshold (Fast) Selector. Proceedings from the2014 IEEE International Electron Devices Meeting, San Francisco, CA, December 15–17, 2014; IEEE: New York, 2014; pp 160–163.
14. Liu, T. A 130.7 mm22-Layer 32 Gb ReRAM Memory Device in 24 nm Technology. Proceedings from theInternational Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, February 17–21, 2013; IEEE: New York, 2013; pp 210–212.
15. Fackenthal, R.; Kitagawa, M.; Otsuka, W.; Prall, K.; Mills, D.; Tsutsui, K.; Javanifard, J.; Tedrow, K.; Tsushima, T.; Shibahara, Y. 19.7 A 16 Gb ReRAM with 200 MB/s Write and 1 GB/s Read in 27 nm Technology. Proceedings from theInternational Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, February 9–13, 2014; IEEE: New York, 2014; pp 338–340.
10.1109/ISSCC.2014.6757460 ↗16. Ito, S.; Hayakawa, Y.; Wei, Z.; Muraoka, S.; Kawashima, K.; Kotani, H.; Kouno, K.; Nakamura, M.; Du, G. A.; Chen, J. F. ReRAM Technologies for Embedded Memory and Further Applications. Proceedings from theInternational Memory Workshop (IMW), Kyoto, Japan, May 13–16, 2018; IEEE: New York, 2018.
10.1109/IMW.2018.8388846 ↗21. International Roadmap for Devices and Systems 2020 Edition; IEEE: New York, 2020. https://irds.ieee.org/editions/2020 (accessed 2021-05-25).
22. Govoreanu, B.; Kar, G.; Chen, Y.; Paraschiv, V.; Kubicek, S.; Fantini, A.; Radu, I.; Goux, L.; Clima, S.; Degraeve, R. 10 × 10 nm2Hf/HfOxCrossbar Resistive RAM with Excellent Performance, Reliability and Low-Energy Operation. Proceedings from theInternational Electron Devices Meeting (IEDM), Washington, DC, December 5–7, 2011; IEEE: New York, 2011; pp 729–732.
24. Levisse, A.; Giraud, B.; Noel, J.P.; Moreau, M.; Portal, J.M. Rram Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. Proceedings from theConference on Design of Circuits and Integrated Systems (DCIS), Lyon, France, November 14–16, 2018; IEEE: New York, 2018.
10.1109/DCIS.2018.8681470 ↗25. Deng, Y.; Chen, H.Y.; Gao, B.; Yu, S.; Wu, S.C.; Zhao, L.; Chen, B.; Jiang, Z.; Liu, X.; Hou, T.H. Design and Optimization Methodology for 3D RRAM Arrays. Proceedings from theInternational Electron Devices Meeting (IEDM), Washington, DC, December 9–11, 2013; IEEE: New York, 2013; pp 629–632.
10.1109/IEDM.2013.6724693 ↗28. Milo, V.; Anzalone, F.; Zambelli, C.; Pérez, E.; Mahadevaiah, M.; Ossorio, Ó.; Olivo, P.; Wenger, C.; Ielmin, D. Optimized Programming Algorithms for Multilevel RRAM in Hardware Neural Networks. Proceedings from theInternational Reliability Physics Symposium (IRPS), Monterey, CA, March 21–25, 2021; IEEE: New York, 2021.
10.1109/IRPS46558.2021.9405119 ↗29. Grenouillet, L.; Castellani, N.; Persico, A.; Meli, V.; Martin, S.; Billoint, O.; Segaud, R.; Bernasconi, S.; Pellissier, C.; C. Jahan, C.; CharpinNicolle, C.; Dezest, P.; Carabasse, C.; Besombes, P.; Ricavy, S.; Tran, N.P.; Magalhaes-Lucas, A.; Roman, A.; Boixaderas, C.; Magis, T.; Bedjaoui, M.; Tessaire, A.; Seignard, F.; Mazen, S.; Landis, M.; Vianello, E.; Molas, G.; Gaillard, F.; Arcamone, J.; Nowak, E. 16kbit 1T1R OxRAM Arrays Embedded in 28 nm FDSOI Technology Demonstrating Low BER, High Endurance, and Compatibility with Core Logic Transistors. Proceedings from theInternational Memory Workshop (IMC), Dresden, Germany, May 16–19, 2021; IEEE: New York, 2021.
10.1109/IMW51353.2021.9439607 ↗30. Nail, C.; Molas, G.; Blaise, P.; Piccolboni, G.; Sklenard, B.; Cagli, C.; Bernard, M.; Roule, A.; Azzaz, M.; Vianello, E.; Carabasse, C.; Berthier, R.; Cooper, D.; Pelissier, C.; Magis, T. Understanding RRAM Endurance, Eetention and Window Margin Trade-Off Using Experimental Results and Simulations. Proceedings from theInternational Electron Devices Meeting (IEDM), San Francisco, CA, December 3–7, 2016; IEEE: New York, 2016; pp 95–98.
10.1109/IEDM.2016.7838346 ↗43. Wei, Z.; Katoh, Y.; Ogasahara, S.; Yoshimoto, Y.; Kawai, K.; Ikeda, Y.; Eriguchi, K.; Ohmori, K.; Yoneda, S. True Random Number Generator Using Current Difference Based on a Fractional Stochastic Model in 40-nm Embedded ReRAM. Proceedings from theInternational Electron Devices Meeting (IEDM), San Francisco, CA, December 3–7, 2016; IEEE: New York, 2016; pp 107–110.
10.1109/IEDM.2016.7838349 ↗59. Lienig, J. Electromigration and Its Impact on Physical Design in Future Technologies. Proceedings of the2013 ACM International symposium on Physical Design, Nevada, March 24–27, 2013; ACM: New York, 2013; pp 33–40.
10.1145/2451916.2451925 ↗66. Kund, M.; Beitel, G.; Pinnow, C. U.; Röhr, T.; Schumann, J.; Symanczyk, R.; Ufert, K.; Muller, G. Conductive-Bridging RAM (CBRAM): An Emerging Non-Volatile Memory Technology Scalable to Sub 20 nm. Proceedings from theInternational Electron Devices Meeting. (IEDM), Washington, DC, December 5, 2005; IEEE: New York, 2005; pp 754–757.
78. Lee, J.; Shin, J.; Lee, D.; Lee, W.; Jung, S.; Jo, M.; Park, J.; Biju, K. P.; Kim, S.; Park, S. Diode-Less Nano-Scale ZrOx/HfOxRRAM Device with Excellent Switching Uniformity and Reliability for High-Density Cross-Point Memory Applications. Proceedings from theInternational Electron Devices Meeting (IEDM), San Francisco, CA, December 6–8, 2010; IEEE: New York, 2010; pp 452–455.
10.1109/IEDM.2010.5703393 ↗90. Jo, S. H.; Kumar, T.; Zitlaw, C.; Nazarian, H. Self-Limited RRAM with ON/OFF Resistance Ratio Amplification. Proceedings from theSymposium on VLSI Technology (VLSI Technology), Kyoto, Japan, June 16–18, 2015; IEEE: New York, 2015; pp 128–129.
10.1109/VLSIT.2015.7223715 ↗92. Xu, X.; Tai, L.; Gong, T.; Yin, J.; Huang, P.; Yu, J.; Luo, Q.; Liu, J.; Yu, Z.; Zhu, X. 40 × Retention Improvement by Eliminating Resistance Relaxation with High Temperature Forming in 28 nm RRAM Chip. Proceedings from theInternational Electron Devices Meeting (IEDM), San Francisco, CA, December 1–5, 2018; IEEE: New York, 2018; pp 464–467.
10.1109/IEDM.2018.8614593 ↗93. Chen, C. Y.; Fantini, A., Degraeve, R.; Redolfi, A.; Groeseneken, G.; Goux, L.; Kar, G. S. Statistical Investigation of the Impact of Program History and Oxide-Metal Interface on OxRRAM Retention. Proceedings from theIEEE International Electron Devices Meet. (IEDM), San Francisco, CA, December 3–7, 2016; IEEE: New York, 2016; pp 99–102.
10.1109/IEDM.2016.7838347 ↗97. Lee, H.; Chen, P.; Wu, T.; Chen, Y.; Wang, C.; Tzeng, P.; Lin, C.; Chen, F.; Lien, C.; Tsai, M.J. Low Power and High Speed Bipolar Switching with a Thin Reactive Ti Buffer Layer in Robust HfO2Based RRAM. Proceedings from theIEEE International Electron Devices Meet. (IEDM), San Francisco, CA, December 15–17, 2008; IEEE: New York, 2008.
10.1109/IEDM.2008.4796677 ↗