2D inter-chip optical interconnect

Abstract The main reason for the expected I/O-bottleneck in future data processing systems, is the increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion, EMI) result in an increasing mismatch between silicon processing capabilities and interconnect performance, pushing packaging costs and required effort to significantly higher levels. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European community funded ESPRIT project OIIC (“Optically Interconnected Integrated Circuits”). The central issue of OIIC concerns the area optical interconnect approach to the interconnect bottleneck encountered in advanced VLSI-CMOS designs. The envisaged route to solving this problem offers high-throughput data interconnects on inter-chip and multi-chip module (MCM) level, facilitating implementation of new digital architectures and systems. The OIIC project is aimed towards the realisation of three demonstrators: a system demonstrator with an 8×8 FPGA digital core, implementing state-of-the-art technology, and two link demonstrators, aiming at a high-speed approach with 16 channels (Gigalink), and a low power, high-density approach on 100 μm pitch with 100 channels (Photonlink). For the demonstrators, flexible guided wave optical pathways are used. In this paper, progress and results in the project on architecture, components, optical pathways and mounting techniques are highlighted, with main focus on the system demonstrator.