Strategies of high-accuracy memristor-based analogue computing in memory for artificial intelligence
Source abstract
Abstract
Memristor-based analogue computing in memory (CIM) offers revolutionary gains in energy efficiency and computing power for data-intensive applications such as artificial intelligence. However, it typically struggles with achieving high accuracy at the same time, owing to the noise-sensitive nature of analogue computing and the non-ideal characteristics at the device and circuit levels that inevitably result in computing errors. Although progress has been made in device engineering and hardware-algorithm co-optimization to mitigate the error and parasitic effects, many of these advances inadvertently incur a hardware or energy consumption overhead, undermining the core benefits of analogue CIM. This Review dissects the computing error sources across the CIM hierarchy from the memristor device and array to the system architecture and algorithm, and evaluates the strategies to minimize those errors. We highlight the material and device innovations, array-level techniques and algorithm-architecture co-design frameworks towards high-accuracy analogue CIM. By dissecting the trade-off between computing accuracy and implementation cost, this Review draws a roadmap for translating memristor-based analogue CIM technology from proof-of-concept prototypes to large-scale deployment for accelerating next-generation artificial intelligence.
Source: europepmc · Quality: candidate unverified · Source record ↗
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Energy Harvesting in Wireless Networks
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
References (100+)
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1. Brown, T. B. et al. Language models are few-shot learners. In Proc. 34th International Conference on Neural Information Processing Systems (eds Larochelle, H. et al.) 1877–1901 (Curran Associates, 2020).
2. Gholami, A. et al. AI and memory wall. IEEE Micro 44, 33–39 (2024).10.1109/MM.2024.3373763 ↗
3. McKee, S. A. Reflections on the memory wall. In Proc. 1st Conference on Computing Frontiers 162–167 (Association for Computing Machinery, 2004); https://doi.org/10.1145/977091.97711510.1145/977091.977115 ↗
4. Zhang, W. et al. Neuro-inspired computing chips. Nat. Electron. 3, 371–382 (2020).10.1038/s41928-020-0435-7 ↗
5. Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61–64 (2015).10.1038/nature14441 ↗
6. Li, C. et al. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks. Nat. Commun. 9, 2385 (2018).10.1038/s41467-018-04484-2 ↗
7. Yao, P. et al. Fully hardware-implemented memristor convolutional neural network. Nature 577, 641–646 (2020).10.1038/s41586-020-1942-4 ↗
8. Wan, W. et al. A compute-in-memory chip based on resistive random-access memory. Nature 608, 504–512 (2022).10.1038/s41586-022-04992-8 ↗
9. Zhang, W. et al. Edge learning using a fully integrated neuro-inspired memristor chip. Science 381, 1205–1211 (2023).10.1126/science.ade3483 ↗
10. Chang, M. et al. A 40nm 60.64TOPS/W ECC-capable compute-in-memory/digital 2.25MB/768kB RRAM/SRAM system with embedded Cortex M3 microprocessor for edge recommendation systems. In 2022 IEEE International Solid-State Circuits Conference (ISSCC) 1–3 (IEEE, 2022); https://doi.org/10.1109/ISSCC42614.2022.973167910.1109/ISSCC42614.2022.9731679 ↗
11. Huang, Y. et al. Radiofrequency signal processing with a memristive system-on-a-chip. Nat. Electron. 8, 587–596 (2025).10.1038/s41928-025-01409-y ↗
12. Le Gallo, M. et al. A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference. Nat. Electron. https://doi.org/10.1038/s41928-023-01010-1 (2023).10.1038/s41928-023-01010-1 ↗
13. Ambrogio, S. et al. An analog-AI chip for energy-efficient speech recognition and transcription. Nature 620, 768–775 (2023).10.1038/s41586-023-06337-5 ↗
14. Zhao, H. et al. Implementation of discrete Fourier transform using RRAM arrays with quasi-analog mapping for high-fidelity medical image reconstruction. In 2021 IEEE International Electron Devices Meeting (IEDM) 12.4.1–12.4.4 (IEEE, 2021); https://doi.org/10.1109/IEDM19574.2021.972054710.1109/IEDM19574.2021.9720547 ↗
15. Qin, Q. et al. Hybrid precoding with a fully-parallel large-scale analog RRAM array for 5G/6G MIMO communication system. In 2022 International Electron Devices Meeting (IEDM) 33.2.1–33.2.4 (IEEE, 2022); https://doi.org/10.1109/IEDM45625.2022.1001942610.1109/IEDM45625.2022.10019426 ↗
16. Yang, J. et al. Conditional diffusion model acceleration with first-demonstrated RRAM-based in-memory neural differential equation solver. In 2024 IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024); https://doi.org/10.1109/IEDM50854.2024.1087348710.1109/IEDM50854.2024.10873487 ↗
17. Huang, Y. et al. Memristor-based hardware accelerators for artificial intelligence. Nat. Rev. Electr. Eng. 1, 286–299 (2024).10.1038/s44287-024-00037-6 ↗
18. Aguirre, F. et al. Hardware implementation of memristor-based artificial neural networks. Nat. Commun. 15, 1974 (2024).10.1038/s41467-024-45670-9 ↗
19. Zhang, W. et al. Analog-type resistive switching devices for neuromorphic computing. Phys. Status Solidi Rapid Res. Lett. 13, 1900204 (2019).10.1002/pssr.201900204 ↗
20. Zhao, M., Gao, B., Tang, J., Qian, H. & Wu, H. Reliability of analog resistive switching memory for neuromorphic computing. Appl. Phys. Rev. 7, 011301 (2020).10.1063/1.5124915 ↗
21. Strukov, D. B., Snider, G. S., Stewart, D. R. & Williams, R. S. The missing memristor found. Nature 453, 80–83 (2008).10.1038/nature06932 ↗
22. Yang, J. J. et al. Memristive switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 3, 429–433 (2008).10.1038/nnano.2008.160 ↗
23. Yang, J. J., Strukov, D. B. & Stewart, D. R. Memristive devices for computing. Nat. Nanotechnol. 8, 13–24 (2013).10.1038/nnano.2012.240 ↗
24. McPherson, J., Kim, J.-Y., Shanware, A. & Mogul, H. Thermochemical description of dielectric breakdown in high dielectric constant materials. Appl. Phys. Lett. 82, 2121–2123 (2003).10.1063/1.1565180 ↗
25. Ahn, M. et al. Memristors based on (Zr, Hf, Nb, Ta, Mo, W) high-entropy oxides. Adv. Electron. Mater. 7, 2001258 (2021).10.1002/aelm.202001258 ↗
26. Choi, S. et al. SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations. Nat. Mater. 17, 335–340 (2018).10.1038/s41563-017-0001-5 ↗
27. Mou, X. et al. Analog memristive synapse based on topotactic phase transition for high-performance neuromorphic computing and neural network pruning. Sci. Adv. 7, eabh0648 (2021).10.1126/sciadv.abh0648 ↗
28. Sharma, D. et al. Linear symmetric self-selecting 14-bit kinetic molecular memristors. Nature 633, 560–566 (2024).10.1038/s41586-024-07902-2 ↗
29. Goswami, S. et al. Robust resistive memory devices using solution-processable metal-coordinated azo aromatics. Nat. Mater. 16, 1216–1224 (2017).10.1038/nmat5009 ↗
30. Williams, R. S., Goswami, S. & Goswami, S. Potential and challenges of computing with molecular materials. Nat. Mater. 23, 1475–1485 (2024).10.1038/s41563-024-01820-4 ↗
31. Barlas, M. et al. Improvement of HfO2 based RRAM array performances by local Si implantation. In 2017 IEEE International Electron Devices Meeting (IEDM) 14.6.1–14.6.4 (IEEE, 2017); https://doi.org/10.1109/IEDM.2017.826839210.1109/IEDM.2017.8268392 ↗
32. Hu, R. et al. Nitrogen-oxyanion-doped HfO2 resistive random-access memory with chemically enhanced forming. IEEE Electron Device Lett. 44, 618–621 (2023).10.1109/LED.2023.3250449 ↗
33. Wu, W., Wu, H., Gao, B., Deng, N. & Qian, H. Suppress variations of analog resistive memory for neuromorphic computing by localizing Vo formation. J. Appl. Phys. 124, 152108 (2018).10.1063/1.5037896 ↗
34. Chen, Y.-S. et al. Good endurance and memory window for Ti/HfOx pillar RRAM at 50-nm scale by optimal encapsulation layer. IEEE Electron Device Lett. 32, 390–392 (2011).10.1109/LED.2010.2099201 ↗
35. Wu, W. et al. Improving analog switching in HfOx-based resistive memory with a thermal enhanced layer. IEEE Electron Device Lett. 38, 1019–1022 (2017).10.1109/LED.2017.2719161 ↗
36. Xi, Y. et al. The impact of thermal enhance layers on the relaxation effect in analog RRAM. IEEE Trans. Electron Devices 69, 4254–4258 (2022).10.1109/TED.2022.3183958 ↗
37. Ma, C. et al. Endurance optimization of 40nm RRAM towards 106 cycles by tuning the stoichiometry of TiN bottom electrode. In 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 1–3 (IEEE, 2025); https://doi.org/10.1109/EDTM61175.2025.1104137110.1109/EDTM61175.2025.11041371 ↗
38. Chen, C. Y. et al. Understanding the impact of programming pulses and electrode materials on the endurance properties of scaled Ta2O5 RRAM cells. In 2014 IEEE International Electron Devices Meeting 14.2.1–14.2.4 (IEEE, 2014); https://doi.org/10.1109/IEDM.2014.704704910.1109/IEDM.2014.7047049 ↗
39. Zhao, L. et al. Highly reliable 40nm embedded dual-interface-switching RRAM technology for display driver IC applications. In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 316–317 (IEEE, 2022); https://doi.org/10.1109/VLSITechnologyandCir46769.2022.983028910.1109/VLSITechnologyandCir46769.2022.9830289 ↗
40. Chen, W.-C., Qin, S., Yu, Z. & Wong, H.-S. P. Reduced HfO2 resistive memory variability by inserting a thin SnO2 as oxygen stopping layer. IEEE Electron Device Lett. 42, 1778–1781 (2021).10.1109/LED.2021.3124290 ↗
41. Wang, C. et al. HfOx/AlOy superlattice-like memristive synapse. Adv. Sci. 9, 2201446 (2022).10.1002/advs.202201446 ↗
42. Huang, X. et al. HfO2/Al2O3 multilayer for RRAM arrays: a technique to improve tail-bit retention. Nanotechnology 27, 395201 (2016).10.1088/0957-4484/27/39/395201 ↗
43. Hayakawa, Y. et al. Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application. In 2015 Symposium on VLSI Technology (VLSI Technology) T14–T15 (IEEE, 2015); https://doi.org/10.1109/VLSIT.2015.722368410.1109/VLSIT.2015.7223684 ↗
44. Wang, Q. et al. A logic-process compatible RRAM with 15.43 MB/mm2 density and 10years@150°C retention using STI-less dynamic-gate and self-passivation sidewall. In 2023 International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023); https://doi.org/10.1109/IEDM45741.2023.1041388510.1109/IEDM45741.2023.10413885 ↗
45. Zhang, J. et al. A 28nm 4MB embedded RRAM IP with record-high endurance of 107 cycles and 10 years@125°C retention through reliability-enhanced design-technology co-optimization. In 2024 IEEE International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2024); https://doi.org/10.1109/IEDM50854.2024.1087331110.1109/IEDM50854.2024.10873311 ↗
46. Wen, T.-H. et al. Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing. Science 384, 325–332 (2024).10.1126/science.adf5538 ↗
47. Wu, C.-Y. et al. Emerging memory RRAM embedded in 12FFC FinFET technology for industrial applications. In 2023 International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023); https://doi.org/10.1109/IEDM45741.2023.1041377510.1109/IEDM45741.2023.10413775 ↗
48. Rao, M. et al. Thousands of conductance levels in memristors integrated on CMOS. Nature 615, 823–829 (2023).10.1038/s41586-023-05759-5 ↗
49. Yang, C.-F. et al. Demonstration of high endurance capability on mega-bit RRAM macro and model of ppm level failures. In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 318–319 (IEEE, 2022); https://doi.org/10.1109/VLSITechnologyandCir46769.2022.983037410.1109/VLSITechnologyandCir46769.2022.9830374 ↗
50. Correll, J. M. et al. An 8-bit 20.7 TOPS/W multi-level cell ReRAM-based compute engine. In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 264–265 (IEEE, 2022); https://doi.org/10.1109/VLSITechnologyandCir46769.2022.983049010.1109/VLSITechnologyandCir46769.2022.9830490 ↗
51. Yang, J. et al. 24.2 A 14nm-FinFET 1MB embedded 1T1R RRAM with a 0.022µm2 cell size using self-adaptive delayed termination and multi-cell reference. In 2021 IEEE International Solid-State Circuits Conference (ISSCC) 336–338 (IEEE, 2021); https://doi.org/10.1109/ISSCC42613.2021.936594510.1109/ISSCC42613.2021.9365945 ↗
52. Yin, S., Sun, X., Yu, S. & Seo, J.-S. High-throughput in-memory computing for binary deep neural networks with monolithically integrated RRAM and 90-nm CMOS. IEEE Trans. Electron Devices 67, 4185–4192 (2020).10.1109/TED.2020.3015178 ↗
53. Chen, W.-H. et al. CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors. Nat. Electron. 2, 420–428 (2019).10.1038/s41928-019-0288-0 ↗
54. Cai, F. et al. A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations. Nat. Electron. 2, 290–299 (2019).10.1038/s41928-019-0270-x ↗
55. Golonzka, O. et al. Non-volatile RRAM embedded into 22FFL FinFET technology. In 2019 Symposium on VLSI Technology T230–T231 (IEEE, 2019); https://doi.org/10.23919/VLSIT.2019.877657010.23919/VLSIT.2019.8776570 ↗
56. Xue, C.-X. et al. 24.1 A 1MB multibit ReRAM computing-in-memory macro with 14.6ns parallel MAC computing time for CNN based AI edge processors. In 2019 IEEE International Solid-State Circuits Conference (ISSCC) 388–390 (IEEE, 2019); https://doi.org/10.1109/ISSCC.2019.866239510.1109/ISSCC.2019.8662395 ↗
57. Mochida, R. et al. A 4M synapses integrated analog ReRAM based 66.5 TOPS/W neural-network processor with cell current controlled writing and flexible network architecture. In 2018 IEEE Symposium on VLSI Technology 175–176 (IEEE, 2018); https://doi.org/10.1109/VLSIT.2018.851067610.1109/VLSIT.2018.8510676 ↗
58. Shih, P.-H. et al. High density 7nm FinFET dielectric RRAM in embedded memory applications. In 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–3 (IEEE, 2025); https://doi.org/10.23919/VLSITechnologyandCir65189.2025.1107515310.23919/VLSITechnologyandCir65189.2025.11075153 ↗
59. Tsai, C. Y. et al. A CMOS-compatible 12nm 8MB MLC RRAM enabling producible 2-bit per cell for high energy efficiency compute-in-memory in edge AI applications. In 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–3 (IEEE, 2025); https://doi.org/10.23919/VLSITechnologyandCir65189.2025.1107492410.23919/VLSITechnologyandCir65189.2025.11074924 ↗
60. Park, T. H. et al. Thickness effect of ultra-thin Ta2O5 resistance switching layer in 28 nm-diameter memory cell. Sci. Rep. 5, 15965 (2015).10.1038/srep15965 ↗
61. Xu, X. et al. 40× retention improvement by eliminating resistance relaxation with high temperature forming in 28 nm RRAM chip. In 2018 IEEE International Electron Devices Meeting (IEDM) 20.1.1–20.1.4 (IEEE, 2018); https://doi.org/10.1109/IEDM.2018.861459310.1109/IEDM.2018.8614593 ↗
62. Wong, H.-S. P. et al. Metal–oxide RRAM. Proc. IEEE 100, 1951–1970 (2012).10.1109/JPROC.2012.2190369 ↗
63. Qin, S. et al. 8-layer 3D vertical Ru/AlOxNy/TiN RRAM with mega-Ω level LRS for low power and ultrahigh-density memory. In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 314–315 (IEEE, 2022); https://doi.org/10.1109/VLSITechnologyandCir46769.2022.983016410.1109/VLSITechnologyandCir46769.2022.9830164 ↗
64. Sheridan, P. M. et al. Sparse coding with memristor networks. Nat. Nanotechnol. 12, 784–789 (2017).10.1038/nnano.2017.83 ↗
65. Kim, H., Mahmoodi, M. R., Nili, H. & Strukov, D. B. 4K-memristor analog-grade passive crossbar circuit. Nat. Commun. 12, 5198 (2021).10.1038/s41467-021-25455-0 ↗
66. Shin, S., Kim, K. & Kang, S.-M. Analysis of passive memristive devices array: data-dependent statistical model and self-adaptable sense resistance for RRAMs. Proc. IEEE 100, 2021–2032 (2012).10.1109/JPROC.2011.2165690 ↗
67. Jeong, H. et al. Self-supervised video processing with self-calibration on an analogue computing platform based on a selector-less memristor array. Nat. Electron. 8, 168–178 (2025).
68. Li, C. et al. Analogue signal and image processing with large memristor crossbars. Nat. Electron. 1, 52–59 (2018).10.1038/s41928-017-0002-z ↗
69. Yao, P. et al. Face classification using electronic synapses. Nat. Commun. 8, 15199 (2017).10.1038/ncomms15199 ↗
70. Liu, Q. et al. 33.2 A fully integrated analog ReRAM based 78.4TOPS/W compute-in-memory chip with fully parallel MAC computing. In 2020 IEEE International Solid-State Circuits Conference (ISSCC) 500–502 (IEEE, 2020); https://doi.org/10.1109/ISSCC19947.2020.906295310.1109/ISSCC19947.2020.9062953 ↗
71. Ye, W. et al. A 28-nm RRAM computing-in-memory macro using weighted hybrid 2T1R cell array and reference subtracting sense amplifier for AI edge inference. IEEE J. Solid-State Circuits 58, 2839–2850 (2023).10.1109/JSSC.2023.3280357 ↗
72. Sung, C. H. et al. Resistive-gate RAM: an 1TnR architecture feasible for scaling beyond 16nm CMOS generation. In 2025 IEEE International Reliability Physics Symposium (IRPS) 1–6 (IEEE, 2025); https://doi.org/10.1109/IRPS48204.2025.1098291810.1109/IRPS48204.2025.10982918 ↗
73. Kim, S. et al. Ultrathin (<10nm) Nb2O5/NbO2 hybrid memory with both memory and selector characteristics for high density 3D vertically stackable RRAM applications. In 2012 Symposium on VLSI Technology (VLSIT) 155–156 (IEEE; 2012); https://doi.org/10.1109/VLSIT.2012.624250810.1109/VLSIT.2012.6242508 ↗
74. Zhang, W. et al. Array-level boosting method with spatial extended allocation to improve the accuracy of memristor based computing-in-memory chips. Sci. China Inf. Sci. 64, 160406 (2021).10.1007/s11432-020-3198-9 ↗
75. Song, W. et al. Programming memristor arrays with arbitrarily high precision for analog computing. Science 383, 903–910 (2024).10.1126/science.adi9405 ↗
76. Yu, R. et al. A full-stack memristor-based computation-in-memory system with software-hardware co-development. Nat. Commun. 16, 2123 (2025).10.1038/s41467-025-57183-0 ↗
77. Rasch, M. J. et al. Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. Nat. Commun. 14, 5282 (2023).10.1038/s41467-023-40770-4 ↗
78. Esmanhotto, E. et al. Experimental demonstration of multilevel resistive random access memory programming for up to two months stable neural networks inference accuracy. Adv. Intell. Syst. 4, 2200145 (2022).10.1002/aisy.202200145 ↗
79. Jiang, Z. et al. COPS: an efficient and reliability-enhanced programming scheme for analog RRAM and on-chip implementation of denoising diffusion probabilistic model. In 2023 International Electron Devices Meeting (IEDM) 21.1.1–21.1.4 (IEEE, 2023); https://doi.org/10.1109/IEDM45741.2023.1041376410.1109/IEDM45741.2023.10413764 ↗
80. Zhang, S., Wu, H., Gao, B. & Qian, H. Efficient weight mapping scheme without verification for RRAM based neuromorphic computing. In 2019 China Semiconductor Technology International Conference (CSTIC) 1–3 (IEEE, 2019); https://doi.org/10.1109/CSTIC.2019.875572110.1109/CSTIC.2019.8755721 ↗
81. Aziza, H. et al. Multi-level control of resistive RAM (RRAM) using a write termination to achieve 4 bits/cell in high resistance state. Electronics 10, 2222 (2021).10.3390/electronics10182222 ↗
82. Park, J. et al. TiOx-based RRAM synapse with 64-levels of conductance and symmetric conductance change by adopting a hybrid pulse scheme for neuromorphic computing. IEEE Electron Device Lett. 37, 1559–1562 (2016).10.1109/LED.2016.2622716 ↗
83. Merced-Grafals, E. J., Dávila, N., Ge, N., Williams, R. S. & Strachan, J. P. Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications. Nanotechnology 27, 365202 (2016).10.1088/0957-4484/27/36/365202 ↗
84. Chen, J. et al. Optimization strategy for accelerating multi-bit resistive weight programming on the RRAM array. In 2019 IEEE International Workshop on Future Computing (IWOFC) 1–3 (IEEE, 2019); https://doi.org/10.1109/IWOFC48002.2019.907844710.1109/IWOFC48002.2019.9078447 ↗
85. Milo, V. et al. Accurate program/verify schemes of resistive switching memory (RRAM) for in-memory neural network circuits. IEEE Trans. Electron Devices 68, 3832–3837 (2021).10.1109/TED.2021.3089995 ↗
86. Wang, S. et al. Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity. In 2017 47th European Solid-State Device Research Conference (ESSDERC) 14–17 (IEEE, 2017); https://doi.org/10.1109/ESSDERC.2017.806658010.1109/ESSDERC.2017.8066580 ↗
87. Chen, B. et al. A memristor-based hybrid analog–digital computing platform for mobile robotics. Sci. Robot. 5, eabb6938 (2020).10.1126/scirobotics.abb6938 ↗
88. Puglisi, F. M., Zagni, N., Larcher, L. & Pavan, P. Random telegraph noise in resistive random access memories: compact modeling and advanced circuit design. IEEE Trans. Electron Devices 65, 2964–2972 (2018).10.1109/TED.2018.2833208 ↗
89. Yang, S. et al. Relaxation signal analysis and optimization of analog resistive random access memory for neuromorphic computing. IEEE Trans. Electron Devices 71, 560–566 (2024).10.1109/TED.2023.3339115 ↗
90. Le, B. Q. et al. RADAR: a fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays. IEEE Trans. Electron Devices 68, 4397–4403 (2021).10.1109/TED.2021.3097975 ↗
91. Feng, Y. et al. Improvement of state stability in multi-level resistive random-access memory (RRAM) array for neuromorphic computing. IEEE Electron Device Lett. 42, 1168–1171 (2021).10.1109/LED.2021.3091995 ↗
92. Belmonte, A. et al. Optimization of the write algorithm at low-current (10μA) in Cu/Al2O3-based conductive-bridge RAM. In 2015 45th European Solid State Device Research Conference (ESSDERC) 114–117 (IEEE, 2015); https://doi.org/10.1109/ESSDERC.2015.732472610.1109/ESSDERC.2015.7324726 ↗
93. Fantini, A. et al. Intrinsic program instability in HfO2 RRAM and consequences on program algorithms. In 2015 IEEE International Electron Devices Meeting (IEDM) 7.5.1–7.5.4 (IEEE, 2015); https://doi.org/10.1109/IEDM.2015.740964810.1109/IEDM.2015.7409648 ↗
94. Belmonte, A. et al. Impact of temperature and programming method on the data retention of Cu/Al2O3-based conductive-bridge RAM operated at low-current (10 μA). Solid State Electron. 125, 189–197 (2016).10.1016/j.sse.2016.07.015 ↗
95. Milo, V. et al. Optimized programming algorithms for multilevel RRAM in hardware neural networks. In 2021 IEEE International Reliability Physics Symposium (IRPS) 1–6 (IEEE, 2021); https://doi.org/10.1109/IRPS46558.2021.940511910.1109/IRPS46558.2021.9405119 ↗
96. Le, B. Q. et al. Resistive RAM with multiple bits per cell: array-level demonstration of 3 bits per cell. IEEE Trans. Electron Devices 66, 641–646 (2019).10.1109/TED.2018.2879788 ↗
97. Jiang, Z. et al. Reliability-enhanced reverse forming operation scheme for analog resistive random-access memory. IEEE Electron Device Lett. 46, 199–202 (2025).10.1109/LED.2024.3521924 ↗
98. He, W. et al. PRIVE: efficient RRAM programming with chip verification for RRAM-based in-memory computing acceleration. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) 1–6 (IEEE, 2023); https://doi.org/10.23919/DATE56975.2023.1013726610.23919/DATE56975.2023.10137266 ↗
99. Le Gallo, M. et al. Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars. Neuromorphic Comput. Eng. 2, 014009 (2022).10.1088/2634-4386/ac4fb7 ↗
100. Ma, C. et al. Go unary: a novel synapse coding and mapping scheme for reliable ReRAM-based neuromorphic computing. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) 1432–1437 (IEEE, 2020); https://doi.org/10.23919/DATE48585.2020.911655510.23919/DATE48585.2020.9116555 ↗