Through-Silicon-Via Interposers with Cu-Level Electrical Conductivity and Si-Level Thermal Expansion Based on Carbon Nanotube-Cu Composites for Microelectronic Packaging Applications

Through-silicon-via (TSV) interposers using silicon and copper represent a critical element in microelectronic packaging, as they bridge between fine-pitch inputs/outputs at the integrated circuit chips to the coarser-pitch packages at the substrate. High electrical conductivity is one of the required properties, but as with the continued miniaturization of electronics, thermal expansion match between the substrate (typically silicon) and copper becomes increasingly important to avoid device failure. A CNT-Cu composite TSV interposer was fabricated envisioning microelectronic packaging applications, which demonstrates both copper-level electrical conductivity (∼2.5 × 105 S/cm) and Si-level coefficient of thermal expansion (CTE) (∼7 × 10–6/K). The CTE mismatch between CNT-Cu and Si was measured to be less than 1/5 compared with that between Cu and Si. To realize this, numerous technologies were combined. Specifically, this included the precision synthesis of vertically aligned pillars perfectly normal to the growth substrate, structural reinforcement of the CNT bundles to retain alignment during processing, electrodeposition of Cu into the interstitial spaces of the CNT pillars, and insertion of the CNT-Cu pillar arras into a prefabricated TSV substrate. Finally, the functionality of the prepared CNT-Cu TSV interposer was demonstrated for several configurations.