A breakthrough in contact engineering for sub-3 nm FinFETs: overcoming the fin-pitch bottleneck

Abstract We report a breakthrough in contact engineering that overcomes the long-standing fin-pitch (FP) bottleneck, enabling FinFET scaling to sub-3 nm nodes, including feasibility at the 10 Å node. We propose an I-shaped source/drain (S/D) architecture for FinFETs to replace the conventional diamond-shaped S/D, minimizing lateral protrusion while preserving the electrical performance. Calibrated 3D technology computer-aided design simulations show that, despite the reduced contact area, the proposed design sustains—or even improves—ON-state current with comparable subthreshold swing relative to conventional counterparts. Under fixed cell-area targets representative of the 2 nm node, coordinated co-optimization of contacted poly pitch (CPP) and FP reallocates the FP-liberated area margin to moderate CPP expansion, which in turn enables gate-length extension, stronger electrostatic control, and robust suppression of short-channel effects. Sensitivity analyses across realistic specific contact resistivity confirm process-window robustness. Collectively, these results decouple FP scaling from S/D geometry and establish a manufacturing-friendly path to sub-3 nm FinFETs without wholesale architectural changes, such as a transition to gate-all-around architectures.