SRAM Designing with Comparative Analysis using Planer and Non-Planer Nanodevice

The scaling of planer devices is a significant concern for the electronics industry. As the device execution for the performance is estimated with drive current, this mainly depends on gate capacitance. Therefore, a new technology node with reduced size reduces the thickness of the oxide insulator and enhances the gate capacitance. Hence, the drain current increases, enhancing the device performance. Shrinking the geometry brings down applied voltage and frequencies, but device leakage is increasing constantly which is a major challenge. With the nanometer technology, CMOS based circuit isn't preferred because of the issue in its fundamental material, as well as the short channel effect. Along with these issues, better technologies are needed to deal with the various effects of planer devices. To reduce SCE, designers were concentrating on non-planar devices like FINFET, having negligible SCE and same channel length. Conventionally, FINFET has received increasing attention with vertical channel structure because of degraded short channel behavior. FINFET is designed on conventional as well as SOI wafers. Several methods are carried out to reduce SCE in FINFETs, which disclosed that DIBL generated leakage current is well suppressed. This paper reveals that FINFET is considered to reduce SCEs and to design memory device SRAM.