Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p+ poly–n+ poly–p+ poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson–Schrödinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.