A nanoscale scalable memory architecture for molecular electronics

In this paper, we present a nanoscale memory architecture for molecular electronics. A large memory is designed as a collection of smaller molecular-based crossbar subarrays, each of which realizes a part of the large memory. Redundancies at the row/column level in each subarray and at the subarray level are used to tolerate defects generated during the nanofabrication process. Spare subarrays with address translation in the CMOS layer are used to cope with the expected high rate of defects in chemically fabricated nanocircuits. Molecular crossbars on top of a silicon-based die providing address translation will demonstrate a notable improvement in the scalability of defect-prone molecular memories.