Oxide Impurities in Silicon Oxide Intermetal Dielectrics and Their Potential to Elevate Via-Resistances

Abstract Silicon oxide used as an intermetal dielectric (IMD) incorporates oxide impurities during both its formation and subsequent processing to create vias in the IMD. Without a sufficient degassing of the IMD, oxide impurities released from the IMD during the physical vapor deposition (PVD) of the glue layer of the vias had led to an oxidation of the glue layer and eventual increase of the via resistances, which correlated with the O-to-Si atomic ratio of the IMD being ~10% excessive as verified by transmission electron microscopy (TEM) analysis. A vacuum bake of the IMD was subsequently implemented to enhance outgassing of the oxide impurities in the IMD before the glue layer deposition. The implementation successfully reduced the via resistances to an acceptable level.