journal article·2026-04-14

Highly Reliable and Magnetic-Field-Immune Physically Unclonable Functions Using One-Time Programming in SOT-MRAM Arrays

Min Wang, Chuanpeng Jiang, Bi Wang, Yuanfu Zhao, Zhaohao Wang, Weisheng Zhao

Publisher page

Abstract

Spin–orbit torque magnetic random-access memory (SOT-MRAM) is a promising nonvolatile memory technology, offering low power consumption and high-speed read/write performance. The inherent fabrication variations within SOT units generate static entropy, making them suitable as carriers of physically unclonable functions (PUFs). Integrating PUFs with SOT-MRAM chips enhances hardware security and improves the fabrication feasibility, area efficiency, and cost-effectiveness. In this work, we present a highly reliable SOT-MRAM-based PUF design, where the introduction of one-time programmable significantly enhances PUF reliability, such as a 44× improvement in read margin, an optimal inter/intra-Hamming distance ratio, and zero bit error rate. Furthermore, the proposed OTP-PUF exhibits exceptional resilience to external magnetic fields (up to 500 Oe) and stable readout across an extended temperature range (−55 °C–150 °C), guaranteeing reliability in harsh environments. The results demonstrate that SOT-MRAM-based OTP-PUF presents a promising solution for secure memory systems.
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: Physical Unclonable Functions (PUFs) and Hardware Security · Integrated Circuits and Semiconductor Failure Analysis · Security and Verification in Computing

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

School of Integrated Circuit Science and Engineering

Beihang University

Beijing Microelectronics Technology Institute

Funding

National Key Research and Development Program of China · National Natural Science Foundation of China

References (40)

Show source-provided references
1. 10.1002/adma.20220536510.1002/adma.202205365 ↗
2. 10.1109/MCAS.2017.271330510.1109/MCAS.2017.2713305 ↗
3. Tehranipoor M. H. · 202310.1007/978-3-031-19185-5 ↗
4. 10.1109/TED.2021.313836510.1109/TED.2021.3138365 ↗
5. 10.1109/JSSC.2018.288635010.1109/JSSC.2018.2886350 ↗
6. 10.1109/JSSC.2021.312525510.1109/JSSC.2021.3125255 ↗
7. 10.1109/jiot.2024.339948210.1109/jiot.2024.3399482 ↗
8. 10.1109/TED.2017.275586710.1109/TED.2017.2755867 ↗
9. 10.1109/tifs.2015.242148110.1109/tifs.2015.2421481 ↗
10. 10.1016/j.eng.2024.12.02810.1016/j.eng.2024.12.028 ↗
11. Ding, Q.; Jiang, H.; Li, J.; Liu, C.; Yu, J.; Chen, P.; Zhao, Y.; Ding, Y.; Gong, T.; Yang, J.; Unified 0.75 pJ/Bit TRNG and attack resilient 2F 2 /Bit PUF for robust hardware security solutions with 4-layer stacking 3D NbO x threshold switching array. In 2021 IEEE International Electron Devices Meeting (IEDM) ; IEEE, 2021, pp 39.10.1109/IEDM19574.2021.9720641 ↗
12. 10.1002/aelm.20230019510.1002/aelm.202300195 ↗
13. 10.1063/1.504179310.1063/1.5041793 ↗
14. 10.1109/TMAG.2021.307858310.1109/TMAG.2021.3078583 ↗
15. 10.1038/s41565-019-0607-710.1038/s41565-019-0607-7 ↗
16. Honjo, H.; Nguyen, T.; Watanabe, T.; Nasuno, T.; Zhang, C.; Tanigawa, T.; Miura, S.; Inoue, H.; Niwa, M.; Yoshiduka, T.; First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology. In 2019 IEEE International Electron Devices Meeting (IEDM) ; IEEE, 2019, pp 28.10.1109/IEDM19573.2019.8993443 ↗
17. Jiang, C.; Lu, S.; Zhang, Z.; Fan, X.; Xiong, D.; Li, J.; Liu, H.; Wang, G.; Zhang, H.; Jin, H.; Demonstration of 128 Kb SOT-MRAM Chip with 5 ns Write and 15 ns Read Speed, High Endurance Over 10 10 and Low ECC-on Bit Error Rate. In 2024 IEEE International Electron Devices Meeting (IEDM) ; IEEE, 2024, pp 1–4.10.1109/IEDM50854.2024.10873510 ↗
18. 10.1002/aelm.20190019810.1002/aelm.201900198 ↗
19. 10.1088/1674-4926/44/12/12250110.1088/1674-4926/44/12/122501 ↗
20. 10.7567/JJAP.56.04CN0710.7567/JJAP.56.04CN07 ↗
21. 10.1109/led.2025.358153010.1109/led.2025.3581530 ↗
22. Yasin, F.; Palomino, A.; Kumar, A.; Pica, V.; Van Beek, S.; Talmelli, G.; Nguyen, V.; Cosemans, S.; Crotti, D.; Wostyn, K.; Extremely scaled perpendicular SOT-MRAM array integration on 300mm wafer. In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ; IEEE, 2024, pp 1–2.10.1109/VLSITechnologyandCir46783.2024.10631340 ↗
23. Shi, L.; Hou, Z.; Guo, T.; Li, P.; Jiang, C.; Cao, K.; Wang, Z.; Zhao, W.; Wang, B. Physical Unclonable Function Chip based on SOT-MRAM in 180 nm CMOS Technology. In 2023 IEEE Nanotechnology Materials and Devices Conference (NMDC) ; IEEE, 2023, pp 134–138.10.1109/NMDC57951.2023.10343683 ↗
24. Li, P.; Hou, Z.; Gao, H.; Wang, B.; Wang, Z. A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM. In Proceedings of the 18th ACM International Symposium on Nanoscale Architectures ; IEEE, 2023, pp 1–4.10.1145/3611315.3633260 ↗
25. 10.1109/TCSII.2023.333184210.1109/TCSII.2023.3331842 ↗
26. 10.1145/327466610.1145/3274666 ↗
27. Van Beek, S.; O’Sullivan, B. J.; Couet, S.; Crotti, D.; Linten, D.; Kar, G. S. Understanding and empirical fitting the breakdown of MgO in end-of-line annealed MTJs. In 2020 IEEE International Reliability Physics Symposium (IRPS) ; IEEE, 2020, pp 1–5.10.1109/IRPS45951.2020.9129551 ↗
28. 10.1016/S0304-8853(01)00768-510.1016/S0304-8853(01)00768-5 ↗
29. Yau, J.B.; Gibson, G. W.; Hybrid cryogenic memory cells for superconducting computing applications. In 2017 IEEE International Conference on Rebooting Computing (ICRC) ; IEEE, 2017, pp 1–3.10.1109/ICRC.2017.8123684 ↗
30. Zhang, Z.; Fan, X.; Xiong, D.; Sun, H.; Shang, X.; Man, B.; Zhang, C.; Li, S.; Su, R.; Sun, C.; Process optimization and cryogenic evaluation of spin-orbit torque magnetic random access memory. In 2024 IEEE International Memory Workshop (IMW) ; IEEE, 2024, pp 1–4.10.1109/IMW59701.2024.10536970 ↗
31. 10.1103/physrevb.73.13440310.1103/physrevb.73.134403 ↗
32. 10.1109/TMAG.2010.204535410.1109/TMAG.2010.2045354 ↗
33. 10.1109/TCSI.2014.232733710.1109/TCSI.2014.2327337 ↗
34. Wang, L.Y.; Chen, K.J.; Yuh, P.F.; Wang, Y.; Chang, J.; King, Y.C.; Lin, C. J. A New Ultra-Low Voltage Metal Fuse for High Density OTP Applications. In 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) ; IEEE, 2024, pp 1–2.10.1109/VLSITSA60681.2024.10546348 ↗
35. 10.1109/TED.2021.312288510.1109/TED.2021.3122885 ↗
36. Hsieh, E.; Huang, Z.; Chung, S. S.; Ke, J.; Yang, C.; Tsai, C.; Yew, T. The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown. In 2015 IEEE International Electron Devices Meeting (IEDM) ; IEEE, 2015, pp 3–4.10.1109/IEDM.2015.7409619 ↗
37. 10.1109/TED.2023.323750810.1109/TED.2023.3237508 ↗
38. Basu, J.; Taneja, S.; Rajanna, V. K.; Wang, T.; Alioto, M. ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ; IEEE, 2023, pp 1–2.10.23919/VLSITechnologyandCir57934.2023.10185261 ↗
39. Pang, Y.; Gao, B.; Wu, D.; Yi, S.; Liu, Q.; Chen, W.H.; Chang, T.W.; Lin, W. E.; Sun, X.; Yu, S.; A reconfigurable RRAM physically unclonable function utilizing post-process randomness source with< 6 × 10 –6 native bit error rate. In 2019 IEEE International Solid-State Circuits Conference-(ISSCC) ; IEEE, 2019, pp 402–404.10.1109/ISSCC.2019.8662307 ↗
40. 10.1126/sciadv.abn775310.1126/sciadv.abn7753 ↗