journal article·2023-02-28

Machine Learning Application for Output Capacitance Accuracy Improvement: A Case Study for Combinational Cells

Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, Aimad El Mourabit

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Abstract

The lack of physical information at the early gate-level Netlist makes timing accuracy a significant challenge. Advancing in the physical design flow reduces the timing inaccuracy gap in the cell’s delay estimation, where the physical layout information is no longer estimated. This paper aims to improve the cell delay accuracy of Oasys-RTL Synthesis by predicting the cell’s output capacitance using Machine Learning algorithms. We trained and tested various ML Regression algorithms to predict the Oasys-RTL cell’s output capacitance using several 16 nm designs. With the help of a state-of-art tool, APRISA P &R by Siemens EDA, we derived accurate output capacitance values and compared the inaccuracy and error margins between postplaced APRISA and postplaced Oasys-RTL Netlists before and after applying ML models. We reached the highest accuracy using the Random Forest model. The RF model has achieved a total average accuracy of 93.04 % and has reduced the RMSE from 2.537 to 0.655 .
Source: openalex_inverted_index · Quality: baseline

Research context

OpenAlex topics: VLSI and Analog Circuit Testing · Low-power high-performance VLSI design · Semiconductor materials and devices

SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.

Affiliations

Siemens EDA/CSD Calypto - Synthesis Solutions, Rabat, 10010, Morocco

Information, Communication and Embedded Systems (ICES) Team, Mohammed V University, Rabat, 10010, Morocco

System & Data Engineering Team, ENSA of Tangier, Abdelmalek Essaâdi UniversityTangier, 90000, Morocco

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