Design Insights of Multilayer MoS₂ Fin-Shaped FETs for Digital and Analog/RF Applications

The planar MoS 2 MOSFETs have been extensively studied, while the potential of multilayer fin-shaped FETs (known as FinFETs) for scaling and dual/top gate operations remains overlooked. This study examines the digital, analog/RF, and circuit performance of multilayer MoS 2 FinFETs by optimizing the gate metal work function (Φ m = 4.2 eV to 4.5 eV) for dual-gate and top-gate configurations, aligning with the International Roadmap for Devices and Systems (IRDS) N1 node requirements, particularly for the 2028 targets. Using the nonequilibrium Green’s Function (NEGF) method and self-consistent solutions of the Poisson equation and Density Gradient models, it is observed that dual-gate MoS 2 FinFETs outperform their top-gate counterparts in terms of digital performance, with improvements in the I on / I off ratio (∼1 decade) and subthreshold swing (SS) (∼32.5% reduction) at a higher Φ fin of 4.5 eV. To investigate the impact of miniaturization, gate length ( L g ) and fin width ( W fin ) are varied from 10 to 14 nm and 5 to 10 nm, respectively, revealing significant enhancements in performance with downscaling. Analog metrics, including transconductance ( g m ) and voltage gain ( A v ), improve by 17.4% and 32.2%, respectively, while RF metrics, such as cutoff frequency ( f T ) (gate capacitance ( C gg )), increase (decrease) by 47.5% (22.3%) as L g decreases from 14 to 10 nm. In addition, to observe the suitability of the designed device to be adopted into digital, analog/RF applications, a common source (CS) amplifier, Resistive Load inverter, and Ring Oscillator are designed. The CS amplifier produced better gain at lower L g (∼6.33) and higher W fin (∼6.87). These findings serve as a reference for developing next-generation nanoelectronic devices with MoS 2 FinFETs from device to circuit level.