Show source-provided references
21. Ha, Y. H.; Yi, J. H.; Horii, H.; Park, J. H.; Joo, S. H.; Park, S. O.; U-In Chung; Moon, J. T. An Edge Contact Type Cell for Phase Change RAM Featuring Very Low Power Consumption. In 2003 Symposium on VLSI Technology; Kyoto, Japan, June 10–12, 2003; pp 175–176.10.1109/VLSIT.2003.1221142
10.1109/VLSIT.2003.1221142 ↗22. Pellizzer, F.; Benvenuti, A.; Gleixner, B.; Kim, Y.; Johnson, B.; Magistretti, M.; Marangon, T.; Pirovano, A.; Bez, R.; Atwood, G. A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications. In 2006 Symposium on VLSI Technology; Honolulu, HI, USA, June 13–15, 2006; pp 122–123.10.1109/VLSIT.2006.1705247
10.1109/VLSIT.2006.1705247 ↗23. Pirovano, A.; Pellizzer, F.; Tortorelli, I.; Harrigan, R.; Magistretti, M.; Petruzza, P.; Varesi, E.; Erbetta, D.; Marangon, T.; Bedeschi, F.; Fackenthal, R.; Atwood, G.; Bez, R. Self-Aligned MTrench Phase-Change Memory Cell Architecture for 90nm Technology and Beyond. In ESSDERC 2007–37th European Solid State Device Research Conference; Munich, Germany, September 11–13, 2007; pp 222–225.10.1109/ESSDERC.2007.4430918
10.1109/ESSDERC.2007.4430918 ↗24. Chen, W. S.; Hsiao, T. C.; Yeh, J. T.; Chiou, S. H.; Liu, M. Y.; Wang, T. C.; Chein, L. L.; Huang, C. M.; Shih, N. T.; Tu, L. S.; Huang, D.; Lee, C. M.; Yu, T. H.; Kao, M. J.; Tsai, M.J.; Chao, D. S.; Chen, Y. C.; Chen, F.; Chen, C. W.; Yen, P. H.; Chen, M. J.; Wang, W. H. A Novel Cross-Spacer Phase Change Memory with Ultra-Small Lithography Independent Contact Area. In 2007 IEEE International Electron Devices Meeting (IEDM); Washington, DC, USA, December 10–12, 2007; pp 319–322.10.1109/IEDM.2007.4418935
10.1109/IEDM.2007.4418935 ↗25. Breitwisch, M.; Nirschl, T.; Chen, C. F.; Zhu, Y.; Lee, M. H.; Lamorey, M.; Burr, G. W.; Joseph, E.; Schrott, A.; Philipp, J. B.; Cheek, R.; Happ, T. D.; Chen, S. H.; Zaidi, S.; Flaitz, P.; Bruley, J.; Dasaka, R.; Rajendran, B.; Rossnagel, S.; Yang, M.; Chen, Y. C.; Bergmann, R.; Lung, H. L.; Lam, C. Novel Lithography-Independent Pore Phase Change Memory. In 2007 Symposium on VLSI Technology; Kyoto, Japan, June 12–14, 2007; pp 100–101.10.1109/VLSIT.2007.4339743
10.1109/VLSIT.2007.4339743 ↗26. Ahn, S. J.; Hwang, Y. N.; Song, Y. J.; Lee, S. H.; Lee, S. Y.; Park, J. H.; Jeong, C. W.; Ryoo, K. C.; Shin, J. M.; Park, J. H.; Fai, Y.; Oh, J. H.; Koh, G. H.; Jeong, G. T.; Joo, S. H.; Choi, S. H.; Son, Y. H.; Shin, J. C.; Kim, Y. T.; Jeong, H. S.; Kim, K. Highly Reliable 50nm Contact Cell Technology for 256Mb PRAM. In 2005 Symposium on VLSI Technology; Kyoto, Japan, June 14–16, 2005; pp 98–99.10.1109/.2005.1469227
10.1109/.2005.1469227 ↗27. Kim, I. S.; Cho, S. L.; Im, D. H.; Cho, E. H.; Kim, D. H.; Oh, G. H.; Ahn, D. H.; Park, S. O.; Nam, S. W.; Moon, J. T.; Chung, C. H. High Performance PRAM Cell Scalable to Sub-20nm Technology with below 4F2 Cell Size, Extendable to DRAM Applications. In 2010 Symposium on VLSI Technology; Honolulu, HI, USA, June 15–17, 2010; pp 203–20410.1109/VLSIT.2010.5556228.
10.1109/VLSIT.2010.5556228 ↗28. Hwang, Y. N.; Lee, S. H.; Ahn, S. J.; Lee, S. Y.; Ryoo, K. C.; Hong, H. S.; Koo, H. C.; Yeung, F.; Oh, J. H.; Kim, H. J.; Jeong, W. C.; Park, J. H.; Horii, H.; Ha, Y. H.; Yi, J. H.; Koh, G. H.; Jeong, G. T.; Jeong, H. S.; Kim, K. Writing Current Reduction for High-Density Phase-Change RAM. In 2003 IEEE International Electron Devices Meeting (IEDM); Washington, DC, USA, December 8–10, 2003; pp 37.1.1–37.1.410.1109/IEDM.2003.1269422.
10.1109/IEDM.2003.1269422 ↗29. Lee, J. I.; Park, H.; Cho, S. L.; Park, Y. L.; Bae, B. J.; Park, J. H.; Park, J. S.; An, H. G.; Bae, J. S.; Ahn, D. H.; Kim, Y. T.; Horii, H.; Song, S. A.; Shin, J. C.; Park, S. O.; Kim, H. S.; Chung, U.In.; Moon, J. T.; Ryu, B. I. Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation. In 2007 Symposium on VLSI Technology; Kyoto, Japan, June 12–14, 2007; pp 102–10310.1109/VLSIT.2007.4339744.
10.1109/VLSIT.2007.4339744 ↗30. Im, D. H.; Lee, J. I.; Cho, S. L.; An, H. G.; Kim, D. H.; Kim, I. S.; Park, H.; Ahn, D. H.; Horii, H.; Park, S. O.; Chung, U.I.; Moon, J. T. A Unified 7.5nm Dash-Type Confined Cell for High Performance PRAM Device. In 2008 IEEE International Electron Devices Meeting (IEDM); San Francisco, CA, USA, December 15–17, 2008; pp 1–410.1109/IEDM.2008.4796654.
10.1109/IEDM.2008.4796654 ↗31. Kang, M. J.; Park, T. J.; Kwon, Y. W.; Ahn, D. H.; Kang, Y. S.; Jeong, H.; Ahn, S. J.; Song, Y. J.; Kim, B. C.; Nam, S. W.; Kang, H. K.; Jeong, G. T.; Chung, C. H. PRAM Cell Technology and Characterization in 20nm Node Size. In 2011 IEEE International Electron Devices Meeting (IEDM); Washington, DC, USA, December 05–07, 2011; pp 3.1.1–3.1.410.1109/IEDM.2011.6131478.
10.1109/IEDM.2011.6131478 ↗33. Rao, M. C.; Ravindranadh, K.; Shekhawat, M. S. Structural and Electrical Properties of TiO2 Thin Films. In AIP Conference Proceedings; 2016, Vol. 1728, no. 02007710.1063/1.4946128.
10.1063/1.4946128 ↗44. Landau L. D. · 1984 · 8
56. Pirovano, A.; Lacaita, A. L.; Benvenuti, A.; Pellizzer, F.; Hudgens, S.; Bez, R. Scaling Analysis of Phase-Change Memory Technology. In 2003 IEEE International Electron Devices Meeting (IEDM); Washington, DC, USA, December 8–10, 2003; pp 29.6.1–29.6.410.1109/IEDM.2003.1269376.
10.1109/IEDM.2003.1269376 ↗57. Sasago, Y.; Kinoshita, M.; Morikawa, T.; Kurotsuchi, K.; Hanzawa, S.; Mine, T.; Shima, A.; Fujisaki, Y.; Kume, H.; Moriya, H.; Takaura, N.; Torii, K. Cross-Point Phase Change Memory with 4F2 Cell Size Driven by Low-Contact-Resistivity Poly-Si Diode. In 2009 Symposium on VLSI Technology; Kyoto, Japan June 15–17, 2009; pp 24–25.
58. Im, D. H.; Lee, J. I.; Cho, S. L.; An, H. G.; Kim, D. H.; Kim, I. S.; Park, H.; Ahn, D. H.; Horii, H.; Park, S. O.; Chung, U.I.; Moon, J. T. A Unified 7.5nm Dash-Type Confined Cell for High Performance PRAM Device. In 2008 IEEE International Electron Devices Meeting (IEDM); San Francisco, CA, USA, December 15–17, 2008; pp 1–410.1109/IEDM.2008.4796654.
10.1109/IEDM.2008.4796654 ↗