Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching
Source abstract
Abstract
This study presents a straightforward approach for fabricating heterogeneous complementary FET (CFET) devices. The process flow commences with a SiGe/Ge/Si epitaxial multilayer structure grown on a SOI substrate. The source/drains for both stacked devices were straightforwardly performed through P and B implantations with precise depth control, respectively. The isolation of the top p-SiGe FET from the bottom n-Si FET was achieved by etching away the middle Ge sacrificial layer and subsequently filled with SiO 2 dielectric material. The etching selectivity of Ge over Si and Si 0.8 Ge 0.2 by utilizing a H 2 O 2 solution was nearly infinite, resulting in a flawless structure with p-SiGe channels stacked over n-Si channels. Finally, a functional CFET inverter device composed of a top inversion mode (IM) SiGe nanosheet pFET and a bottom IM Si nanosheet nFET was demonstrated.
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Research context
OpenAlex topics: Advancements in Semiconductor Devices and Circuit Design · Nanowire Synthesis and Applications · Semiconductor materials and devices
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Taiwan Semiconductor Research Institute, National Applied Research Laboratories, Hsinchu 30076, Taiwan
School of Integrated Science and Technology (ISI), Sirindhorn International Institute of Technology (SIIT), Thammasat University, Pathum Thani 12120, Thailand
References (12)
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