Al-Doped Rutile TiO ₂ with Y ₂ O ₃ –ZrO ₂ Stacks Achieving Thin Thickness and Low Leakage for Dynamic Random-Access Memory Capacitors

High Resolution Image Download MS PowerPoint Slide This study investigates Al-doped TiO 2 /Y 2 O 3 /ZrO 2 trilayer capacitors grown by atomic layer deposition as a feasible material to scale high- k dielectric films for dynamic random-access memory (DRAM) capacitors. An ultrathin Y 2 O 3 insertion layer (<0.5 nm) at the TiO 2 /ZrO 2 interface facilitated the formation of a high- k tetragonal/cubic–like ZrO 2 phase at ultrathin thicknesses, as verified by equivalent oxide thickness (EOT)–physical oxide thickness (POT) analysis, grazing-incidence X-ray diffraction, and transmission electron microscopy analysis. Such an enhanced crystallization enabled achieving a higher bulk k at a smaller POT and improved leakage properties. Postmetallization annealing (PMA) conditions were optimized for back-end-of-line compatibility, with PMA at 400 °C for 30 s in N 2 providing adequate interfacial curing, minimal EOT increase, and a lower leakage current. In contrast, PMA at 400 °C for 30 min resulted in EOT growth driven by intermixing, and PMA at 600 °C for 30 s enhanced crystallinity but increased leakage due to grain-boundary-assisted conduction. Temperature-dependent transport revealed that the dominant mechanism is bulk-limited Poole–Frenkel emission in the ZrO 2 layer for both bias polarities, while the leakage magnitude is modulated by asymmetric injection conditions at the Ru/Al-doped TiO 2 and ZrO 2 /TiN interfaces. Poole–Frenkel analysis yielded a consistent trap depth of ∼1.1 eV and physically reasonable optical dielectric constants for ZrO 2 -based dielectrics. With Y 2 O 3 insertion and short-time PMA at 400 °C, the Al-doped TiO 2 /Y 2 O 3 /ZrO 2 film achieved a minimum EOT of ∼0.63 nm at a POT of ∼6.0 nm, outperforming other ZrO 2 -based stacks at comparable thickness while maintaining acceptable leakage. Overall, interfacial Y 2 O 3 insertion combined with optimized PMA provided a practical pathway to achieve a lower POT at a given EOT in rutile TiO 2 -based next-generation DRAM capacitors.