Resistive Memristor Coupled with Multilevel Perpendicular Magnetic States
Source abstract
Abstract
Memristor is an increasingly important research field for in-memory computing (IMC) due to its significant potential in neuromorphic computing. A resistive memristor that can integrate components with nonvolatility and high-density features, such as spintronics, would be a great blessing for the IMC technology. We demonstrate a Pt/Co/NiO device that exhibited multilevel perpendicular exchange bias (EB) with resistive switching (RS) behaviors. It arose from the modulated Co-NiO exchange coupling with the formation/breaking of the conductive filament (CF) within the NiO layer. With atomistic simulation, we show that the multilevel RS stemmed from the modulation of CF size and distribution at the Co–NiO interface, which in turn influenced intermediate levels of EB along the perpendicular direction. It illustrates the possibility of integrating resistive memristors and spintronic devices. Compared with similar studies, our device possesses the advantages of perpendicular magnetic anisotropy and tunable unipolar/bipolar switching.
Source: openalex_inverted_index · Quality: baseline
Research context
OpenAlex topics: Advanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Transition Metal Oxide Nanomaterials
SciVX discovery tags are terminology-based. OpenAlex topics are source-provided classifications.
Affiliations
Department of Materials Science & Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan
Funding
National Science and Technology Council · Ministry of Education, Taiwan
References (60)
Show source-provided references
1. 10.3390/electronics909141410.3390/electronics9091414 ↗
2. Shahsavari, M.; Boulet, P. Memristor Nanodevice for Unconventional Computing: Review and Applications, arXiv:1703.00331. arXiv.org e-Print archive https://arxiv.org/abs/1703, 2017.
3. Lee, S. R.; Kim, Y.; Chang, M.; Kim, K. M.; Lee, C. B.; Hur, J. H.; Park, G. S.; Lee, D.; Lee, M.; Lee, M. J.; Kim, C. J.; Kim, C. J.; Chung, U.; Chung, U. I.; Yoo, I.; Yoo, I. K.; Kim, K. Multi-Level Switching of Triple-Layered TaOx RRAM with Excellent Reliability for Storage Class Memory, 2012 Symposium VLSI Technology, 2012; pp 71–72.10.1109/VLSIT.2012.6242466 ↗
4. 10.1063/1.492244610.1063/1.4922446 ↗
5. 10.3390/nano1213218510.3390/nano12132185 ↗
6. 10.3390/nano1102031510.3390/nano11020315 ↗
7. 10.1109/LED.2018.278942510.1109/LED.2018.2789425 ↗
8. 10.1109/LED.2018.282170710.1109/LED.2018.2821707 ↗
9. 10.1109/TED.2016.261564810.1109/TED.2016.2615648 ↗
10. 10.1088/0957-4484/27/43/43570110.1088/0957-4484/27/43/435701 ↗
11. 10.1088/2053-1591/ab154d10.1088/2053-1591/ab154d ↗
12. 10.1016/j.ceramint.2022.11.12210.1016/j.ceramint.2022.11.122 ↗
13. 10.1021/acsaelm.3c0038710.1021/acsaelm.3c00387 ↗
14. 10.1002/adma.20190063610.1002/adma.201900636 ↗
15. 10.1002/adfm.20180810410.1002/adfm.201808104 ↗
16. 10.1038/s41928-020-0385-010.1038/s41928-020-0385-0 ↗
17. 10.1002/aisy.20200018210.1002/aisy.202000182 ↗
18. 10.1002/adfm.20210787010.1002/adfm.202107870 ↗
19. 10.1002/adma.20210367210.1002/adma.202103672 ↗
20. Pearson W. B. · 1958
21. 10.1002/adma.20210529010.1002/adma.202105290 ↗
22. 10.1002/advs.20190276710.1002/advs.201902767 ↗
23. 10.1002/adma.20180188510.1002/adma.201801885 ↗
24. 10.1063/1.133075210.1063/1.1330752 ↗
25. 10.1103/PhysRevB.57.1162310.1103/PhysRevB.57.11623 ↗
26. 10.1039/D3CP03106C10.1039/D3CP03106C ↗
27. 10.1063/1.512950610.1063/1.5129506 ↗
28. 10.1021/acsami.2c0576410.1021/acsami.2c05764 ↗
29. 10.1063/1.489148210.1063/1.4891482 ↗
30. 10.1063/1.281361710.1063/1.2813617 ↗
31. 10.1039/C4NR04394D10.1039/C4NR04394D ↗
32. 10.1063/1.348988210.1063/1.3489882 ↗
33. 10.1063/1.487591810.1063/1.4875918 ↗
34. 10.1063/1.327542610.1063/1.3275426 ↗
35. 10.1063/1.495546610.1063/1.4955466 ↗
36. Russo, U.; Ielmini, D.; Cagli, C.; Lacaita, A. L.; Spiga, S.; Wiemer, C.; Perego, M.; Fanciulli, M. Conductive-Filament Switching Analysis and Self-Accelerated Thermal Dissolution Model for Reset in NiO-Based RRAM, Technical Digest - International Electron Devices Meeting IEDM, 2007; pp 775–778.10.1109/IEDM.2007.4419062 ↗
37. 10.1021/nl401563810.1021/nl4015638 ↗
38. 10.1021/acsnano.2c0435610.1021/acsnano.2c04356 ↗
39. 10.1016/j.ceramint.2020.06.05110.1016/j.ceramint.2020.06.051 ↗
40. 10.1116/1.124774910.1116/1.1247749 ↗
41. 10.1016/j.cattod.2017.08.04110.1016/j.cattod.2017.08.041 ↗
42. 10.1002/sia.554910.1002/sia.5549 ↗
43. 10.1021/acsami.1c1268310.1021/acsami.1c12683 ↗
44. Niu, D.; Zou, Q.; Xu, C.; Xie, Y. Low Power Multi-Level-Cell Resistive Memory Design with Incomplete Data Mapping, 2013 IEEE 31st International Conference on Computer Design ICCD 2013, 2013; pp 131–137.10.1109/ICCD.2013.6657035 ↗
45. Xu, C.; Niu, D.; Naveen, M.; Jouppi, N. P.; Xie, Y. Understanding the Trade-Offs in Multi-Level Cell ReRAM Memory Design, 2013 50th ACM/EDAC/Annual Design Automation Conference (DAC), Austin, TX, USA, 2013; pp 1–6.10.1145/2463209.2488867 ↗
46. 10.1088/1361-6528/aae2ff10.1088/1361-6528/aae2ff ↗
47. 10.1109/LED.2013.223888310.1109/LED.2013.2238883 ↗
48. 10.1038/srep0578010.1038/srep05780 ↗
49. Kang, J. F.; Li, H. T.; Huang, P.; Chen, Z.; Gao, B.; Liu, X. Y.; Jiang, Z. Z.; Wong, H. S. P. Modeling and Design Optimization of ReRAM, 20th Asia South Pacific Des. Autom. Conf. ASP-DAC 2015, 2015; pp 576–581.10.1109/ASPDAC.2015.7059070 ↗
50. 10.1007/s10854-023-09881-y10.1007/s10854-023-09881-y ↗
51. 10.1088/0953-8984/26/10/10320210.1088/0953-8984/26/10/103202 ↗
52. 10.1109/TMAG.2015.249062610.1109/TMAG.2015.2490626 ↗
53. 10.1515/rams-2019-001410.1515/rams-2019-0014 ↗
54. 10.1063/1.502014810.1063/1.5020148 ↗
55. 10.3389/fmats.2020.0001710.3389/fmats.2020.00017 ↗
56. 10.1557/jmr.2019.35310.1557/jmr.2019.353 ↗
57. 10.1109/TED.2009.202404610.1109/TED.2009.2024046 ↗
58. 10.1007/s10854-015-2848-z10.1007/s10854-015-2848-z ↗
59. Zhang S. · Adv. Electron. Mater. · 2019 · 5 · 180078210.1002/aelm.201800782 ↗
60. 10.1063/1.493097110.1063/1.4930971 ↗