Low Interface Resistance in Epitaxial β-Ga₂O₃ Vertical Power Diodes on Silicon (100) Using TiN Buffer

Integrating Ga 2 O 3 power electronics on a silicon substrate can reduce the system cost and improve heat dissipation, but high on-resistance in vertical power devices is its major drawback. We solve this challenge with an electrically conductive epitaxial TiN (100) buffer layer that can be deposited on Si (100) without SiO x formation. While our thin MgO interlayer strategy prevents GaTiO x at the TiN-Ga 2 O 3, it also results in a large vertical resistance. By tailoring the Ga 2 O 3:Si “seed layer” deposition process, we achieve a state-of-the-art on-resistance of 3.3 mΩ cm 2 in epitaxial Ga 2 O 3 (100) diodes on Si (100), setting an upper bound for Ga 2 O 3 /TiN interface resistance. Temperature-dependent leakage analysis suggests its primary source is Poole-Frenkel emission of electrons from defect levels 0.57 eV below the conduction band.