Electron and Hole Trapping Characteristics of a Low-Temperature Atomic Layer-Deposited HfO₂ Charge-Trap Layer for Charge-Trap Flash Memory

Scaling down the charge-trap memory cell for high storage density causes severe reliability issues such as the decreased trapped charge density, migration of stored charges to adjacent cells, electrostatic interference between neighboring cells, and gate dielectric breakdown. Therefore, it is highly required to explore the advanced charge-trap layer (CTL) having a high trap density with a deep level for improved performance and reliability. In this study, nonvolatile charge-trap memory characteristics are demonstrated using a low-temperature atomic layer deposition (ALD) of hafnium oxide (HfO 2 ) CTL and Al 2 O 3 tunneling and blocking oxides. The use of a high- k dielectric stack enhances the electric field for efficient and reliable device operations in scaled-down devices. In particular, the low-temperature ALD HfO 2 CTL deposited at 50 °C has a high charge-trap areal density of 9.65 × 10 12 cm –2, exhibiting a large threshold voltage shift of ∼5 V. The proposed device presents a nonvolatile retention of 81.7% for 10 h thanks to the amorphous phase of the low-temperature HfO 2 CTL, in contrast to a poor retention of 44.8% in the device with the crystalline high-temperature HfO 2 CTL deposited at 200 °C. Furthermore, rapid thermal annealing at 600 °C on the dielectric stack significantly enhances hole trapping in the HfO 2 CTL via creation of acceptor-level traps by interdiffusion between HfO 2 and Al 2 O 3, securing the large threshold voltage shift of ∼7.8 V. It paves the way for providing the optimized gate dielectric stack of CTF consisting of Al 2 O 3 and defective HfO 2 for improved CTF characteristics.